AN2647 datasheet(28/34 Pages) STMICROELECTRONICS

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Interfacing with synchronous memory

AN2647

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Synchronous burst mode

PSRAM BCR register configuration for synchronous burst mode

For a system that requires high speed data transfer, you have to configure the PSRAM and

the EMI bus to operate in synchronous burst mode. Before writing to the PSRAM BCR (Bus

Configuration Register) to set up burst mode, the CRE signal must be driven high by writing

a 1 to GPIO pin P6.0. After the configuration, CRE must be set to low to return to normal bus

operation. The BCR configuration bus cycle operates in asynchronous mode and is

described in the previous section.

Table 9. shows the BCR configuration bit values. When writing to BCR, the register gets the

write data value not from the data bus input, but rather from the address lines A[21:0]. The

BCR data must then be embedded in your EMI address. Please note the internal 32-bit

ARM address is a byte aligned address. Before it is driven to the EMI bus, the address lines

are right shifted by one and is converted to a half-word (16-bit) aligned address.

After the PSRAM BCR register is configured for burst mode, the EMI bus also need to be re-

configured from asynchronous to synchronous burst mode. An EMI burst cycle consists of

an asynchronous access to read or write the first halfword and then followed by multiple

burst cycles, where each data transfer takes only one BCLK clock to complete. The timings

of the first access in a burst cycle are the same as defined in asynchronous mode.

EMI bus configuration for synchronous burst mode

Table 10 shows the EMI bus registers and control bits for synchronous mode operation. The

configuration is similar to the asynchronous mode, with the following additional bits are set

in the EMI_BCR register:

Table 9.

PSRAM bus configuration register bit setting for burst mode

bit

Bit name

Bit

value

Function

21:20

reserved

19:18

Select BCR

Select BCR as target register

17:16

reserved

Operating mode

Synchronous Burst access(default=1, asynchronous

access)

Initial latency

Fixed Latency; first access time in a burst cycle

13:11

Latency counter

100

Set to code 4

Wait polarity

Active low

9reserved

Wait configuration

Asserted one data cycle before delay (default)

7:6

reserved

5:4

Drive strength

½ (default)

Burst Wrap

Burst no wrap (default)

2:0

Burst length

111

Continuous Burst (default)

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