AN2647 datasheet(24/34 Pages) STMICROELECTRONICS

No. de pieza	AN2647

Descripción Electrónicos	Using the STR91xFA external memory interface

PDF	34 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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24 / 34 page

Interfacing with synchronous memory

AN2647

24/34

Figure 12. and Figure 13. show typical PSRAM asynchronous read and write bus cycles

using ADV# to latch the address. The EMI bus is configured to match the PSRAM timing and

input signal waveform. The EMI_ALE is configured as active low with a 2 tBCLK pulse width

to meet the ADV# address setup and hold time. The EMI_UBn and EMI_LBn are enabled by

setting the Byte_En bit in the SCU_EMI register and the BLE bit in the EMI_BCR register.

The EMI_WEn and EMI_RDn are configured with enough wait state to meet the 70ns of

read and write access time of the MT45W4M.

Note:

Setting the EMI_ALE_LNGT bit in SCU_SCR0 selects an EMI ALE length of Two clock

cycles in asynchronous mode but one and a half clock cycles in synchronous Mode.

Figure 13.

PSRAM asynchronous write using ADV# (EMI_ALE)

AN2647 Datasheet(PDF) 24 Page - STMicroelectronics