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AN2647 Datasheet(PDF) 14 Page - STMicroelectronics

No. de pieza AN2647
Descripción Electrónicos  Using the STR91xFA external memory interface
PDF  34 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN2647 Datasheet(HTML) 14 Page - STMicroelectronics

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Interfacing with asynchronous memory
AN2647
14/34
bit bus cycles. The bus cycle is identical to the standard 8-bit cycle except the EMI_CS chip
select signal stays low during the consecutive write cycles. Figure 9. shows the bus timings
when CPU executes a halfword write instruction (STRH) followed by a LDRH instruction.
Note the EMI_CS signal stays low throughout the two write bus cycles. The two bytes that
are read in the LDRH cycles are combined into one halfword in the EMI block before being
transferred to the CPU.
Figure 9.
Halfword write and read bus cycles in 8-bit non-multiplexed mode
Page mode timing
The EMI bus in non-Multiplexed mode can be configured to support memory with Page
mode. When in Page mode data are transferred in burst of four, eight or sixteen bytes. The
Page mode bit and the data transfer size is specified in the EMI_BCRx register.
The configuration of the EMI_RDn signal timing is the same as in asynchronous read
cycles. When page mode is enabled, the read cycle consists of an asynchronous read,
followed by multiple burst reads of one byte per BCLK clock. The EMI_RDn and chip select
signal will automatically be extended and stay active until the end of the last page read.
If the page mode access time of your memory device plus the EMI data setup time (tRDS) is
more than one BCLK period, you need to insert burst read wait state in the EMI_BRDCRx
register.
1.2
Other EMI bus configurations
After the bus read/write bus timing configuration is determined, the next step is to set up the
Bus Control register and other GPIO port control registers to support the bus type that you
selected (Mux or Non_Mux).
1.2.1
Bus control register (BCR)
Each of the memory banks has its own Bus Control register that specifies the bus operating
mode. The bits that need to be configured for asynchronous memory read and write are
listed in Table 3.. Some of the register bits that are dedicated for synchronous bus mode are
not included in the table.



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