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AN2647 Datasheet(PDF) 27 Page - STMicroelectronics |
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AN2647 Datasheet(HTML) 27 Page - STMicroelectronics |
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27 / 34 page ![]() AN2647 Interfacing with synchronous memory 27/34 EMI read and write asynchronous bus cycle The EMI configurations in Table 8 will generate the write and read timing as shown in Figure 14. The EMI_ALE signal, which indicates the start of a bus cycle, is connected to the ADV# pin. The MT45W4M latches the address "33h" at the rising edge of EMI_ALE, and then latches the write data "CDh" at the rising edge of EMI_WEn. Please note the MT45W4M ignores the inputs on its address pins after the address latching. This allows the EMI to take over the AD bus and drive the data "CDh". Figure 14. EMI bus write and read bus cycles in asynchronous mode Note: For your reference an asynchronous software example is delivered with this application note. |
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