PM0056 datasheet(68/156 Pages) STMICROELECTRONICS

68 / 156 page

The Cortex-M3 instruction set

PM0056

68/156

DocID15491 Rev 5

The PUSH and POP instructions can be expressed in this form (see PUSH and POP for

details).

Restrictions

In these instructions:

•

Rn must not be PC

•

reglist must not contain SP

•

In any STM instruction, reglist must not contain PC

•

In any LDM instruction, reglist must not contain PC if it contains LR

•

reglist must not contain Rn if you specify the writeback suffix

When PC is in reglist in an LDM instruction:

•

bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch

occurs to this halfword-aligned address.

•

If the instruction is conditional, it must be the last instruction in the IT block

Condition flags

These instructions do not change the flags.

Examples

LDMR8,{R0,R2,R9}; LDMIA is a synonym for LDM

STMDBR1!,{R3-R6,R11,R12}

Incorrect examples

STMR5!,{R5,R4,R9}; value stored for R5 is unpredictable

LDMR2, {}; there must be at least one register in the list

3.4.7

PUSH and POP

Push registers onto, and pop registers off a full-descending stack.

Syntax

PUSH{cond} reglist

POP{cond} reglist

where:

•

‘cond’ is an optional condition code (see Conditional execution on page 57)

•

‘reglist’ is a non-empty list of registers, enclosed in braces. It can contain register

ranges. It must be comma-separated if it contains more than one register or register

range (see Examples on page 68).

PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory

addresses for the access based on SP, and with the final address for the access written

back to the SP. PUSH and POP are the preferred mnemonics in these cases.

PM0056 Datasheet(PDF) 68 Page - STMicroelectronics

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