PM0056 datasheet(31/156 Pages) STMICROELECTRONICS

31 / 156 page

DocID15491 Rev 5

31/156

PM0056

The Cortex-M3 processor

2.2.7

Synchronization primitives

The Cortex-M3 instruction set includes pairs of synchronization primitives. These provide a

non-blocking mechanism that a thread or process can use to obtain exclusive access to a

memory location. Software can use them to perform a guaranteed read-modify-write

memory update sequence, or for a semaphore mechanism.

A pair of synchronization primitives comprises:

The pairs of Load-Exclusive and Store-Exclusive instructions are:

•

The word instructions LDREX and STREX

•

The halfword instructions LDREXH and STREXH

•

The byte instructions LDREXB and STREXB.

Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive

instruction.

To perform a guaranteed read-modify-write of a memory location, software must:

Use a Load-Exclusive instruction to read the value of the location.

Update the value, as required.

Use a Store-Exclusive instruction to attempt to write the new value back to the memory

location, and tests the returned status bit. If this bit is:

0: The read-modify-write completed successfully,

1: No write was performed. This indicates that the value returned at step 1 might

be out of date. The software must retry the read-modify-write sequence,

A Load-Exclusive instruction

Used to read the value of a memory location, requesting

exclusive access to that location.

A Store-Exclusive instruction

Used to attempt to write to the same memory location,

returning a status bit to a register. If this bit is:

0: it indicates that the thread or process gained

exclusive access to the memory, and the write

succeeds

1: it indicates that the thread or process did not gain

exclusive access to the memory, and no write is

performed

PM0056 Datasheet(PDF) 31 Page - STMicroelectronics