RM0319 datasheet(55/368 Pages) STMICROELECTRONICS

55 / 368 page

RM0319

Multiport DDR controller (MPMC)

Doc ID 022640 Rev 3

55/368

6.2

Main features

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Multichannel AHB interfaces:

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Five independent AHB ports

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Separate AHB memory controller programming interface

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Supports all AHB burst types

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Lock transactions are not supported

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Port queue post multiple AHB transactions

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Internal efficient port arbitration scheme to ensure high memory bandwidth utilization.

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Fully pipelined read - write commands

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Advanced bank look-ahead features for high memory throughput

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Programmable register interface to control memory device parameters and protocols

including the following main functionalities:

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Auto pre-charge

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Read/write grouping

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Bank splitting

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Bank grouping

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Swapping

–Aging

●

Full initialization of memory on memory controller reset

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DRAM controller supports both DDR-Mobile and DDR2 memory devices:

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DDR Mobile up to 166 MHz (333 MT/sec)

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DDR2 up to 333 MHz (666 MT/sec)

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Memory frequency with DLL enable configured within range from 100 MHz to 333 MHz.

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Controller supports:

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Wide range of memory device: 128 MBit, 256 MBit, 512 MBit, 1 MBit, 2 MBit

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Two chip selects

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Memory data with 8 or 16 bits

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