RM0319 datasheet(92/368 Pages) STMICROELECTRONICS

92 / 368 page

Multiport DDR controller (MPMC)

RM0319

92/368

Doc ID 022640 Rev 3

The reset signal for the memory controller core is the asynchronous active-low reset rst_n

signal that resets all critical flip-flops in the system to ensure the memory controller core

exits from reset in a known state.

When the memory controller core is reset all parameters are reset too, so any commands

inside the memory controller core are lost. Resetting the core does not automatically reset

the AHB ports: resetting the memory controller core without AHB port reset will generate

unknown behavior.

The AHB port reset is the active-low asynchronous signal ahbX_HRESETn. When this reset

is asserted, the associated AHB port will be reset. The port FIFOs will be cleared and the

pointers will be reset. To prevent corruption within the memory controller, AHB ports should

only be reset at initialization and while the port is idle at the interface and with no commands

within the memory controller core.

During initialization, it is recommended that both resets be asserted simultaneously. The

memory controller core reset should be removed first, followed by the port reset. The reset

should be asserted for at least 5 cycles.

6.6

Programming examples

6.6.1

Initializing the MPMC controller

After power on, once the power supply to memory devices and the device itself is stable, the

memory controller must be initialized: afterward it will automatically initialize the memory

devices.

The procedure to initialize the memory controller is as follows:

Clear the rst_n signal by driving it to 1'b0. All programmable registers will be cleared.

Set the rst_n signal synchronously with the memory controller clock by driving the

signal to 1'b1.

Issue write register commands to configure the DRAM protocols and the settings for

the DCC. Keep the start parameter de-asserted during this initialization step.

Assert the start parameter. This triggers the memory controller to execute the

initialization sequence using the parameters written into the registers.

The memory controller will automatically initialize the DRAM memory devices and lock the

internal DCC. The DLL will process and send a signal to the initialization block when it has

locked.

For more information on register configuration, please refer to the Application note

(AN3100): Configuring the SPEAr3xx multiport memory controller (MPMC) for external DDR

SDRAM, present on www.st.com.

RM0319 Datasheet(PDF) 92 Page - STMicroelectronics