RM0319 datasheet(123/368 Pages) STMICROELECTRONICS

123 / 368 page

RM0319

USB 2.0 Device ports (UDC)

Doc ID 022640 Rev 3

123/368

In this scenario, all endpoint TxFIFOs are mapped to the system memory, and the

application writes the data directly to the endpoint TxFIFOs. Similarly, the RxFIFO is also

mapped to the system memory, and the application reads directly from the RxFIFO.

11.3.9

DMA (AHB master interface)

Enabling the UDC-AHB Subsystem to become an AHB master (that is, entering the DMA

mode, Section 11.4.1: DMA mode), the DMA block receives the required data pointers from

the values programmed in the CSRs (Section 11.3.7: Control and status registers), and it

can transfer data with the system memory.

In particular, the DMA supports a true scatter/gather memory distribution, where each

endpoint memory structure is implemented as a linked-list (as detailed in Section 11.4.1:

DMA mode).

The DMA block (which is inactive in slave-only mode) consists of three basic components:

●

The DMA transfer engine, which moves the actual data,

●

The DMA controller, which controls the movement of the data,

●

The AHB interface, which manages the flow of data between the DMA and AHB for

both data transfer and CSRs accesses.

11.3.10

DMA transfer engine

The DMA transfer engine is a slave to the DMA by the DMA controller for the actual data

transfer to and from system memory.

In case of a memory access, the DMA transfer engine interfaces with the FIFOs and the

AHB interface module of DMA, and indicates to the DMA whether or not the transfer was

successful. If the data transfer was unsuccessful, the DMA transfer engine also indicates

how many bytes were successfully transferred to the destination, so that the DMA can

decide whether to retry the transaction.

In case of data transfer from the FIFOs to system memory, the DMA transfer engine

depends on status signals from the FIFOs’ respective FIFO controllers. In case of

transferring the data to system memory, the DMA transfer engine registers the data, then

waits for the request from the DMA controller and decides on the direction of the transfer. It

completes the transfer whether the transaction is completed successfully or if there is an

error during the data transfer.

11.3.11

DMA controller

The DMA controller is in charge of all data exchange between FIFOs and system memory.

Specifically, the DMA controller actually consists of two distinct controllers with the aim to

manage both in (transmit) and out (receive) transactions simultaneously, although transmit

and receive functions cannot be performed simultaneously.

From a functional perspective, the DMA controller parses the descriptor structures and then

commands the other subsystem blocks to perform data transfers accordingly. The

descriptors fetched from memory are stored by the DMA controller in a proper descriptors

buffer.

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