ICS874S02I datasheet(6/16 Pages) IDT

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ICS874S02I

1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

IDT™ / ICS™ LVDS CLOCK GENERATOR

ICS874S02BMI REV. AOCTOBER 16, 2008

Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C

NOTE 1: VIL should not be less than -0.3V.

NOTE 2: Common mode input voltage is defined as VIH.

Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C

Table 5. Input Frequency Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C

Table 6. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal

equilibrium has been reached under these conditions.

NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked

and the input reference frequency is stable.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

IIH

Input High Current

CLK, FB_IN

VDD = VIN = 3.465V

150

µA

nCLK, nFB_IN

VDD = VIN = 3.465V

µA

IIL

Input Low Current

CLK, FB_IN

VDD = 3.465V, VIN = 0V

-10

µA

nCLK, nFB_IN

VDD = 3.465V, VIN = 0V

-150

µA

VPP

Peak-to-Peak Input Voltage; NOTE 1

0.15

1.3

VCMR

Common Mode Input Voltage; NOTE 1, 2

GND + 0.5

VDD – 0.85

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

VOD

Differential Output Voltage

350

450

550

∆V

VOD Magnitude Change

VOS

Offset Voltage

1.20

1.33

1.45

∆V

VOS Magnitude Change

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

FIN

Input Frequency

CLK/nCLK

PLL_SEL = 1

62.5

1000

MHz

PLL_SEL = 0

1000

MHz

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

fOUT

Output Frequency

62.5

1000

MHz

tsk(Ø)

Static Phase Offset; NOTE 1, 2

PLL_SEL = 1

-100

100

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 2

PLL Lock Time

1ms

tR / tF

Output Rise/Fall Time

20% to 80%

250

odc

Output Duty Cycle

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