ICS874S02I datasheet(1/16 Pages) IDT

No. de pieza	ICS874S02I

Descripción Electrónicos	One differential clock input pair

PDF	16 Pages

Scroll/Zoom	100%

Fabricante Electrónico	IDT [Integrated Device Technology]

Página de inicio	http://www.idt.com

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1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

ICS874S02I

IDT™ / ICS™ LVDS CLOCK GENERATOR

1

ICS874S02BMI REV. AOCTOBER 16, 2008

PLL_SEL

CLK

nCLK

FB_IN

nFB_IN

SEL0

SEL1

SEL2

SEL3

MR

PLL

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

Q

nQ

QFB

nQFB

0

1

÷1, ÷2, ÷4, ÷8,

÷16, ÷32, ÷64

Pullup

Pulldown

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

QFB

nQFB

VDDO

SEL2

FB_IN

nFB_IN

MR

nCLK

CLK

GND

SEL1

SEL0

VDD

PLL_SEL

VDDA

SEL3

GND

Q

nQ

VDDO

General Description

The ICS874S02I is a highly versatile 1:1 Differential-

to-LVDS Clock Generator and a member of the

HiPerClockS™ family of High Performance Clock

Solutions from IDT. The ICS874S02I has a fully

integrated PLL and can be configured as a zero

delay buffer, multiplier or divider, and has an output frequency

range of 62.5MHz to 1GHz. The reference divider, feedback

divider and output divider are each programmable, thereby

allowing for the following output-to-input frequency ratios: 8:1, 4:1,

2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to

achieve “zero delay” between the input clock and the output

clocks. The PLL_SEL pin can be used to bypass the PLL for

system test and debug purposes. In bypass mode, the reference

clock is routed around the PLL and into the internal output

dividers.

Features

• One differential LVDS output pair and

one differential feedback output pair

• One differential clock input pair

• CLK/nCLK can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, SSTL

• Input frequency range: 62.5MHz to 1GHz

• Output frequency range: 62.5MHz to 1GHz

• VCO range: 500MHz - 1GHz

• External feedback for "zero delay" clock regeneration with

configurable frequencies

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Cycle-to-cycle jitter: 35ps (maximum)

• Static phase offset: ±100ps

• Full 3.3V supply mode

• -40°C to 85°C ambient operating temperature

• Available in standard (RoHS 5) package

HiPerClockS™

ICS

ICS874S02I

20-Lead SOIC

7.5mm x 12.8mm x 2.3mm package body

M Package

Top View

Block Diagram

Pin Assignment

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