ICS874S02I

1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

IDT™ / ICS™ LVDS CLOCK GENERATOR

9

ICS874S02BMI REV. AOCTOBER 16, 2008

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter perform-

ance, power supply isolation is required. The ICS874S02I provides

separate power supplies to isolate any high switching noise from

individually connected to the power supply plane through vias, and

0.01µF bypass capacitors should be used for each pin. Figure 1

requires that an additional 10

Ω resistor along with a 10µF bypass

Figure 1. Power Supply Filtering

Wiring the Differential Input to Accept Single-Ended Levels

Figure 2 shows how the differential input can be wired to accept

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock

R2/R1 = 0.609.

Figure 2. Single-Ended Signal Driving Differential Input

3.3V

10

Ω

10µF

.01µF

.01µF

V_REF

Single Ended Clock Input

CLK

nCLK

R1

1K

C1

0.1u

R2

1K