ICS874S02I datasheet(10/16 Pages) IDT

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ICS874S02I

1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

IDT™ / ICS™ LVDS CLOCK GENERATOR

ICS874S02BMI REV. AOCTOBER 16, 2008

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, and

other differential signals. Both signals must meet the VPP and

VCMR input requirements. Figures 3A to 3E show interface

examples for the HiPerClockS CLK/nCLK input driven by the most

common driver types. The input interfaces suggested here are

examples only. Please consult with the vendor of the driver

component to confirm the driver termination requirements. For

example, in Figure 3A, the input termination applies for IDT

HiPerClockS open emitter LVHSTL drivers. If you are using an

LVHSTL driver from another vendor, use their termination

recommendation.

3A. HiPerClockS CLK/nCLK Input Driven by an IDT

Open Emitter HiPerClockS LVHSTL Driver

Figure 3C. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 3E. HiPerClockS CLK/nCLK Input

Driven by a 2.5V SSTL Driver

Figure 3B. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 3D. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVDS Driver

1.8V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVHSTL

IDT

HiPerClockS

LVHSTL Driver

HiPerClockS

Input

125

3.3V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVPECL

HiPerClockS

Input

CLK

nCLK

HiPerClockS

SSTL

2.5V

Zo = 60

Ω

Zo = 60

Ω

2.5V

3.3V

120

CLK

nCLK

HiPerClockS

Input

LVPECL

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

100

LVDS

CLK

nCLK

3.3V

Receiver

Zo = 50

Ω

Zo = 50

Ω

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