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ICS874S02I Datasheet(PDF) 13 Page - Integrated Device Technology |
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ICS874S02I Datasheet(HTML) 13 Page - Integrated Device Technology |
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13 / 16 page ![]() ICS874S02I 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR IDT™ / ICS™ LVDS CLOCK GENERATOR 13 ICS874S02BMI REV. AOCTOBER 16, 2008 Power Considerations This section provides information on power dissipation and junction temperature for the ICS874S02I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS874S02I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • The maximum current at 85°C is as follows: IDD_MAX = 93mA IDDA_MAX = 19mA IDDO_MAX = 36mA • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (93mA + 19mA) = 388.08mW • Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 36mA = 124.74mW Total Power_MAX = 388.08mW + 124.74mW = 512.82mW • 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θ JA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 64.7°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.513W * 64.7°C/W = 118.2°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 7. Thermal Resistance θJA for 20 Lead SOIC, Forced Convection θ JA by Velocity Linear Feet per Minute 0200 500 Multi-Layer PCB, JEDEC Standard Test Boards 64.7°C/W 56.7°C/W 53.5°C/W |
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