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Data Sheet

AD6679

Rev. B | Page 39 of 81

SIGNAL MONITOR

The signal monitor block provides additional information about

the signal being digitized by the ADC. The signal monitor

computes the peak magnitude of the digitized signal. This

information can be used to drive an AGC loop to optimize the

range of the ADC in the presence of real-world signals.

The results of the signal monitor block can be obtained by

reading back the internal values from the SPI port. A global, 24-

bit programmable period controls the duration of the measure-

ment. Figure 62 shows the simplified block diagram of the

signal monitor block.

The peak detector captures the largest signal within the

observation period. This period observes only the magnitude of

the signal. The resolution of the peak detector is a 13-bit value

and the observation period is 24 bits and represents converter

output samples. The peak magnitude is derived by using the

following equation:

Peak Magnitude (dBFS) = 20 log(Peak Detector Value/213)

The magnitude of the input port signal is monitored over a

programmable time period that is determined by the signal

monitor period registers (SMPRs). Only even values of the

SMPR are supported. The peak detector function is enabled by

setting Bit 1 of Register 0x270 in the signal monitor control

activating this mode.

After enabling this mode, the value in the SMPR is loaded into a

monitor period timer that decrements at the decimated clock

rate. The magnitude of the input signal is compared with the

value in the internal magnitude storage register (not accessible

to the user), and the greater of the two is updated as the current

peak level. The initial value of the magnitude storage register is

set to the current ADC input signal magnitude. This comparison

continues until the monitor period timer reaches a count of 1.

When the monitor period timer reaches a count of 1, the 13-bit

peak level value is transferred to the signal monitor holding

monitor period timer is reloaded with the value in the SMPR,

and the countdown is restarted. In addition, the magnitude of

the first input sample is updated in the internal magnitude

storage register, and the comparison and update procedure, as

explained previously, continues.

FROM

MEMORY

MAP

DOWN

COUNTER

COUNT = 1?

MAGNITUDE

STORAGE

FROM

INPUT

SIGNAL

MONITOR

HOLDING

LOAD

CLEAR

COMPARE

A > B

LOAD

TO STATUS± PINS

AND MEMORY MAP

SIGNAL MONITOR

PERIOD REGISTER

(SMPR)

REG 0x271, REG 0x272, REG 0x273

Figure 62. Signal Monitor Block

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