AD6679 datasheet(30/81 Pages) AD

30 / 81 page

AD6679

Data Sheet

Rev. B | Page 30 of 81

THEORY OF OPERATION

The AD6679 has two analog input channels and 14 LVDS

output lane pairs. The AD6679 is designed to sample wide

bandwidth analog signals of up to 2 GHz. The AD6679 is

optimized for wide input bandwidth, high sampling rates,

excellent linearity, and low power in a small package.

The dual ADC cores feature a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth inputs supporting a variety of

user-selectable input ranges. An integrated voltage reference

eases design considerations.

The AD6679 has several functions that simplify the AGC

function in a communications receiver. The programmable

threshold detector allows monitoring of the incoming signal

power using the fast detect bits of the ADC output data stream,

which are enabled and programmed via Register 0x245 through

threshold, the fast detect indicator goes high. Because this

threshold indicator has low latency, the user can quickly reduce

the system gain to avoid an overrange condition at the ADC input.

The LVDS outputs can be configured depending on the decimation

ratio. Multiple device synchronization is supported through the

SYNC± input pins.

ADC ARCHITECTURE

The architecture consists of an input buffered pipelined ADC.

The input buffer provides a termination impedance to the

analog input signal. This termination impedance can be

changed using the SPI to meet the termination needs of the

driver/amplifier. The default termination value is set to 400 Ω. The

equivalent circuit diagram of the analog input termination is

shown in Figure 33. The input buffer is optimized for high

linearity, low noise, and low power.

The input buffer provides a linear high input impedance (for

ease of drive) and reduces the kickback from the ADC. The

quantized outputs from each stage are combined into a final

16-bit result in the digital correction logic. The pipelined

architecture permits the first stage to operate with a new input

sample while the remaining stages operate with the preceding

samples. Sampling occurs on the rising edge of the clock.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD6679 is a differential buffer. The

internal common-mode voltage of the buffer is 2.05 V. The

clock signal alternately switches the input circuit between

sample mode and hold mode. When the input circuit is switched

into sample mode, the signal source must be capable of charging

the sample capacitors and settling within one-half of a clock cycle.

A small resistor, in series with each input, can help reduce the

peak transient current inserted from the output stage of the

driving source. In addition, low Q inductors or ferrite beads can

be placed on each section of the input to reduce high differen-

tial capacitance at the analog inputs and, thus, achieve the

maximum bandwidth of the ADC. Such use of low Q inductors

or ferrite beads is required when driving the converter front end

at high IF frequencies. Place either a differential capacitor or

two single-ended capacitors on the inputs to provide a matching

passive network. This ultimately creates a low-pass filter (LPF)

at the input, which limits unwanted broadband noise. For more

information, refer to the AN-742 Application Note, the AN-827

Application Note, and the Analog Dialogue article “Transformer-

Coupled Front-End for Wideband A/D Converters” (Volume 39,

April 2005) at www.analog.com. In general, the precise values

depend on the application.

For best dynamic performance, match the source impedances

driving VIN+x and VIN−x such that common-mode settling

errors are symmetrical. These errors are reduced by the common-

mode rejection of the ADC. An internal reference buffer creates

a differential reference that defines the span of the ADC core.

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. In the case of the

AD6679, the available span is programmable through the SPI

port from 1.46 V p-p to 2.06 V p-p differential with 2.06 V p-p

differential being the default.

Differential Input Configurations

There are several ways to drive the AD6679, either actively or

passively. However, optimum performance is achieved by

driving the analog input differentially.

For applications in which SNR and SFDR are key parameters,

differential transformer coupling is the recommended input

configuration (see Figure 43 and Figure 44) because the noise

performance of most amplifiers is not adequate to achieve the

true performance of the AD6679.

For low to midrange frequencies, it is recommended to use a

double balun or double transformer network (see Figure 43) for

optimum performance from the AD6679. For higher

frequencies in the second or third Nyquist zone, it is better to

remove some of the front-end passive components to ensure

wideband operation (see Figure 44).

ADC

2pF

10Ω

4pF

0.1µF

10Ω

4pF

0.1µF

25Ω

ETC1-11-13/

MABA007159

1:1Z

Figure 43. Differential Transformer Coupled Configuration for First and

Second Nyquist Frequencies

ADC

25Ω

0.1µF

25Ω

0.1µF

25Ω

MARKI

BAL-0006

BAL-0006SMG

Figure 44. Differential Transformer Coupled Configuration for Second and

Third Nyquist Frequencies

AD6679 Datasheet(PDF) 30 Page - Analog Devices

AD6679 Datasheet(HTML) 30 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Datasheet Descarga

Enlace URL