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Data Sheet

AD6679

Rev. B | Page 13 of 81

CLK+

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

SYNC+

APERTURE DELAY

N + x

N + 33

N + 34

N + 35

A D12/D13±

A D0/D1±

B D12/D13±

B D0/D1±

CONVERTERS

SAMPLE

[N]

VIN±x

OVR

CLK–

SYNC–

OVR+

(OVERRANGE/STATUS BIT)

OVR–

tCLK

tCH

tDCO

tPD

tSKEWF

tSKEWR

CONVERTERS

SAMPLE

[N]

CONVERTERS

SAMPLE

[N + 1]

CONVERTERS

SAMPLE

[N + 1]

CONVERTERS

SAMPLE

[N + 2]

SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF

THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET

S[N – y]

(ODD BITS)

S[N]

(ODD BITS)

S[N – x]

(EVEN BITS)

S[N]

(EVEN BITS)

S[N + 1]

(ODD BITS)

S[N + 1]

(EVEN BITS)

S[N + 2]

(EVEN BITS)

S[N – 1]

(ODD BITS)

S[N – y]

(ODD BITS)

S[N]

(ODD BITS)

S[N – x]

(EVEN BITS)

S[N]

(EVEN BITS)

S[N + 1]

(ODD BITS)

S[N + 1]

(EVEN BITS)

S[N + 2]

(EVEN BITS)

S[N – 1]

(ODD BITS)

STATUS BIT SELECTED BY

OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0]

IN THE REGISTER MAP

Figure 7. Channel Multiplexed (Even/Odd) Mode—Two Virtual Converters (Decimate by 1)

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