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AD6679 Datasheet(PDF) 75 Page - Analog Devices

No. de pieza AD6679
Descripción Electrónicos  135 MHz BW IF Diversity Receiver
PDF  81 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD6679 Datasheet(HTML) 75 Page - Analog Devices

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Data Sheet
AD6679
Rev. B | Page 75 of 81
Reg.
Addr.
(Hex)
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Notes
0x310
DDC 0 control
Mixer
select
0 = real
mixer
1 =
complex
mixer
Gain
select
0 = 0 dB
gain
1 = 6 dB
gain
IF mode
00 = variable IF mode
(mixers and NCO
enabled)
01 = 0 Hz IF mode
(mixer bypassed, NCO
disabled)
10 = fADC/4 Hz IF mode
(fADC/4 downmixing
mode)
11 = test mode (mixer
inputs forced to +FS,
NCO enabled)
Complex
to real
enable
0 =
disabled
1 =
enabled
0
Decimation rate
select
(complex to real
disabled)
11 = decimate by 2
00 = decimate by 4
01 = decimate by 8
10 = decimate by 16
(complex to real
enabled)
11 = decimate by 1
00 = decimate by 2
01 = decimate by 4
10 = decimate by 8
0x00
0x311
DDC 0 input selection
0
0
0
0
0
Q input
select
0 = Ch. A
1 = Ch. B
0
I input
select
0 = Ch. A
1 = Ch. B
0x00
0x314
DDC 0 frequency LSB
DDC 0 NCO FTW[7:0], twos complement
0x00
0x315
DDC 0 frequency MSB
X
X
X
X
DDC 0 NCO FTW[11:8], twos complement
0x00
0x320
DDC 0 phase LSB
DDC 0 NCO POW[7:0], twos complement
0x00
0x321
DDC 0 phase MSB
X
X
X
X
DDC 0 NCO POW[11:8], twos complement
0x00
0x327
DDC 0 output test
mode selection
0
0
0
0
0
Q output
test
mode
enable
0 =
disabled
1 =
enabled
from
Ch. B
0
I output
test
mode
enable
0 =
disabled
1 =
enabled
from
Ch. A
0x00
0x330
DDC 1 control
Mixer
select
0 = real
mixer
1 =
complex
mixer
Gain
select
0 = 0 dB
gain
1 = 6 dB
gain
IF mode
00 = variable IF mode
(mixers and NCO
enabled)
01 = 0 Hz IF mode
(mixer bypassed, NCO
disabled)
10 = fADC/4 Hz IF mode
(fADC/4 downmixing
mode)
11 = test mode (mixer
inputs forced to +FS,
NCO enabled)
Complex
to real
enable
0 =
disabled
1 =
enabled
0
Decimation rate
select
(complex to real
disabled)
11 = decimate by 2
00 = decimate by 4
01 = decimate by 8
10 = decimate by 16
(complex to real
enabled)
11 = decimate by 1
00 = decimate by 2
01 = decimate by 4
10 = decimate by 8
0x00
0x331
DDC 1 input selection
0
0
0
0
0
Q input
select
0 = Ch. A
1 = Ch. B
0
I input
select
0 = Ch. A
1 = Ch. B
0x05
0x334
DDC 1 frequency LSB
DDC 1 NCO FTW[7:0], twos complement
0x00
0x335
DDC 1 frequency MSB
X
X
X
X
DDC1 NCO FTW[11:8], twos complement
0x00
0x340
DDC 1 phase LSB
DDC 1 NCO POW[7:0], twos complement
0x00
0x341
DDC 1 phase MSB
X
X
X
X
DDC1 NCO POW[11:8], twos complement
0x00
0x347
DDC 1 output test
mode selection
0
0
0
0
0
Q output
test
mode
enable
0 =
disabled
1 =
enabled
from
Ch. B
0
I output
test
mode
enable
0 =
disabled
1 =
enabled
from
Ch. A
0x00



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