AD6679 datasheet(33/81 Pages) AD

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Data Sheet

AD6679

Rev. B | Page 33 of 81

reference, or to provide an external 1.0 V reference. When using

an external voltage reference, provide a 1.0 V reference. The

full-scale adjustment is made using the SPI, irrespective of the

reference voltage. For more information on adjusting the full-

scale level of the AD6679, refer to the Memory Map Register

Table section.

The use of an external reference may be necessary, in some

applications, to enhance the gain accuracy of the ADC or

improve thermal drift characteristics. Figure 51 shows the

typical drift characteristics of the internal 1.0 V reference.

–50

TEMPERATURE (°C)

0.9998

0.9999

1.0000

1.0001

1.0002

1.0003

1.0004

1.0005

1.0006

1.0007

1.0008

1.0009

1.0010

Figure 51. Typical V_1P0 Drift

The external reference must be a stable 1.0 V reference. The

ADR130 is a good option for providing the 1.0 V reference.

Figure 55 shows how the ADR130 can be used to provide the

external 1.0 V reference to the AD6679. The gray areas show

unused blocks within the AD6679 while the ADR130 provides

the external reference.

CLOCK INPUT CONSIDERATIONS

For optimum performance, drive the AD6679 sample clock

inputs (CLK+ and CLK−) with a differential signal. This signal

is typically ac-coupled to the CLK+ and CLK− pins via a

transformer or clock drivers. These pins are biased internally

and require no additional biasing.

Figure 52 shows one preferred method for clocking the

AD6679. The low jitter clock source is converted from a single-

ended signal to a differential signal using an RF transformer.

ADC

CLK+

CLK–

0.1µF

100Ω

50Ω

CLOCK

INPUT

1:1Z

Figure 52. Transformer Coupled Differential Clock

Another option is to ac couple a differential CML or LVDS

signal to the sample clock input pins as shown in Figure 53 and

Figure 54.

ADC

CLK+

CLK–

0.1µF

Z0 = 50Ω

33Ω

71Ω

10pF

3.3V

Figure 53. Differential CML Sample Clock

ADC

CLK+

CLK–

0.1µF

50Ω1

100Ω

CLOCK INPUT

LVDS

DRIVER

CLK+

CLK–

50Ω RESISTORS ARE OPTIONAL.

CLOCK INPUT

Figure 54. Differential LVDS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to the clock duty cycle. Commonly, a 5% tolerance

is required on the clock duty cycle to maintain dynamic

performance characteristics. In applications where the clock

duty cycle cannot be guaranteed to be 50%, a higher multiple

frequency clock can be supplied to the AD6679. For example,

the AD6679 can be clocked at 2 GHz with the internal clock

divider set to 4. This ensures a 50% duty cycle, high slew rate

internal clock for the ADC. See the Memory Map section for

more details on using this feature.

FULL-SCALE

VOLTAGE

ADJUST

V_1P0

0.1µF

VOUT 4

SET 5

VIN

GND

ADR130

0.1µF

INPUT

FULL-SCALE

CONTROL

INTERNAL

V_1P0

GENERATOR

Figure 55. External Reference Using the ADR130

AD6679 Datasheet(PDF) 33 Page - Analog Devices

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