CTS9513API-2 datasheet(5/28 Pages) ETC

5 / 28 page

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SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE

Rev E

Tuesday, September 25,

CTS9513-2

5 Chan 16 bit 20MHz Counter/Timer

the output of the previous counter, allowing counter

concatenation and FOUT divided outputs.

Gate Inputs

Gate inputs are used for external hardware triggering

or synchronization of the counters. Each counter may

be programmed to be gated from its own gate line or

the gate lines from the previous or next counter. The

gate lines may also be programmed to be level or

edge sensitive and respond to active high or low

signals.

The gate line may be used to either initiate one or

more count sequences or used as a count enable

line, allowing the counter to count only while the gate

line is held active. Another mode allows the counter

to be reloaded from the load or hold register

depending on the state of the gate line.

PROGRAMMING

Data Bus Operation

Table 3 summarizes the I/O control signal and data

status during bus reads and writes to the CTS9513.

The interface control logic assumes that

• RD and WR are never active simultaneously

• RD, WR, C/D are ignored unless CS is asserted.

Accessing and writing to a specific data or command

Set Data Pointer

Select the appropriate data pointer value

to access the desired register (example

Counter group 1 Mode register 0x01)

Write LOAD DATA POINTER command

to primary command address

(write

0x0001 to device address 0x01) to set

data pointer to Counter Group 1 Mode

This points the data port to the Group 1 mode

least significant word is expected.

WRITING TO REGISTERS

Write Data to Register

If the 16 bit transfer mode is selected, the

next write to the Primary Data Port

(Device Address 0x00) will write data to

the Counter mode register.

If the 8 bit transfer mode is selected, the

next write to the Primary Data Port

Address will expect the least significant

word of the register value, followed by a

write of the most significant word to the

data port. The internal word pointer is

automatically incremented.

If an automatic sequence command has

been

given

the

data

pointer

will

automatically be sequenced to the next

READING REGISTERS

Reading from a device register follows the write

sequence very closely, requiring a write to the

command register to set the appropriate data pointer,

followed by a read or reads from the data port.

Several items should be noted when reading from the

device registers:

The

data

pointer

should

always

reloaded before reading from the data

port if the prior command was anything

but a LOAD DATA POINTER command

in order to update the Read data pre-

fetch latch.

A LOAD DATA POINTER command

should be issued to the device prior to

reading a HOLD register following a

hardware triggered SAVE of the counter

contents to the HOLD register.

COMMANDS

COUNTER COMMANDS

Counter commands are divided into two main groups.

Those commands which directly affect counter

operation, often shortcuts to programming specific

functions,

and

those

associated

with

indirectly addressing the counters’ internal registers.

Counter control commands can be further subdivided

into those commands which affect individual counter

operation and those which affect the overall device

operation.

Table 4 Lists the commands associated with indirect

addressing of the counter internal registers. These

commands point the data port to the appropriate

internal register in order to read or write to them.

Table

Lists

the

commands

associated

with

controlling the actions of individual counters. They

are made up basically of the ARM, DISARM, LOAD,

SAVE, CLEAR, SET and STEP commands.

ARM Command

A counter must be ARMed before it can commence

counting.

Once

ARMed,

counter

may

programmed to begin counting immediately or to

await a hardware trigger to initiate counting.

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