CTS9513API-2 datasheet(7/28 Pages) ETC

7 / 28 page

Celeritous Technical Services Corp

800.687.6510 / 806.793.0708

3308 34th St

FAX

806.793.0710

Lubbock, Texas 79410

http://www.celeritous.com

SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE

Rev E

Tuesday, September 25,

CTS9513-2

5 Chan 16 bit 20MHz Counter/Timer

Figure 6 - CTS9513 Counter Groups 3 - 5

When an output low impedance to ground output is

programmed, the Status bit reflects and Active High

status. When the output is programmed for a high

impedance output or is externally inhibited, the status

summarizes the status register bit assignments.

Master Mode Commands

The Master Mode registers are 16 bit read/Write

registers

used

set

counter

parameters

not

associated

with

individual

counters.

These

parameters include setting the data bus width,

prescaling factors, Time of day functions and data

pointer

sequencing.

The

primary

Master

Mode

device. The auxiliary Master Mode Register is used

to program extended features of the CTS9513. If the

auxiliary register is not programmed the device

behaves as an original ‘9513 device. Table 8

summarizes the primary and auxiliary Master Mode

On Power-up the Master Mode register is cleared to

all zeros resulting in the following default conditions:

Time of Day disabled

Alarm Comparators Disabled

FOUT source is F1

FOUT divider set for divide by 16

FOUT enabled

Data Bus 8 bits

Data Pointer Sequencing enabled

Frequency scaling Binary

Time of Day ( Bits MM0-1)

Bits MM0 and MM1 control the Time-of-day functions

for counters 1 and 2. When enabled, additional

counter logic is enabled to allow the two counters to

operate as a 24 hour clock.

Counters 1 and two must be programmed for BCD

counting. To initialize the time, appropriate values are

loaded in the Counter Load registers. To read the

time a SAVE command is issued to Counters 1 and 2

and the values read from the Hold registers.

Table

illustrates

the

Time-of-day

storage

configuration. In short, Counter 2 bits 8-15 form a

two digit BCD Hours counter, Bits 0-7 form a two digit

BCD Minutes counter. Counter 1 bits Bits 8-15 form

a two digit BCD seconds counter, Bits 4-7 form a

tenth second counter and Bits 0-3 form a division

factor for the input source for divide by 5, 6 or 10.

Comparator Enable (Bits MM2-3)

The two 16 bit comparators on counters 1 and 2 may

be used in any mode. When enabled, the output of

the comparators are routed to the output of the

counter. The output will be asserted when the

comparison between the counter and alarm register

contents are true. It will remain asserted as long as

the counter and alarm register remain the same.

In the Time-of-Day mode the comparators operate in

conjunction such that the output of the counter 2

comparator is asserted only when both comparators

1 and 2 are true. the comparator 1 output will

continue to operate normally.

FOUT Source (Bits MM4-7)

Fifteen different sources may be routed to the input of

the FOUT divider, including the five SOURCE inputs,

five GATE inputs and five of the internal divided

frequencies derived from the X1 input. Additional

Sources may be programmed using the extended

Master mode register functions.

FOUT1 Divider (Bits MM8-11)

FOUT may be divided by 1 to 16. Master mode bits

MM8-11 allow programming of the FOUT divider from

1 to 16 inclusive. Higher order division factors are

programmed through the extended Master Mode

FOUT Enable (Bit MM12)

The FOUT output may be enabled or disabled and

placed in a low impedance state to ground under

software control.

Bus Width (Bit MM13)

When set, this bit places the device into a 16 bit

external data bus mode. When cleared, the external

data bus is set to 8 bits and registers are loaded 8

bits at a time, least significant word first.

Figure 5 - CTS9513 Counter Groups 1 & 2

16 BIT COMPARATOR

16 BIT ALARM REGISTER

16 BIT HOLD REGISTER

16 BIT COUNTER

16 BIT LOAD REGISTER

TERM COUNT

OUTPUT

CNTL

OUT

INT

CNTL

INPUT MUX

CONTROL

COUNTER

CONTROL

MODE

CONTROL

SOURCE

FREQ

GATE

TCN-1

16 BIT HOLD REGISTER

16 BIT COUNTER

16 BIT LOAD REGISTER

TERM COUNT

OUTPUT

CNTL

OUT

INT

CNTL

INPUT MUX

CONTROL

COUNTER

CONTROL

MODE

CONTROL

SOURCE

FREQ

GATE

TCN-1

CTS9513API-2 Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers

CTS9513API-2 Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Descarga

Enlace URL