CTS9513API-2 datasheet(9/28 Pages) ETC

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SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE

Rev E

Tuesday, September 25,

CTS9513-2

5 Chan 16 bit 20MHz Counter/Timer

Count Control (Bits CM3-7)

Whenever the counter reaches a TC, the counter

automatically reloads the counter from the Load or

Hold Register. Which register the counter loads from,

whether the counter counts repeatedly or once,

whether the counter counts binary or BCD and

whether the counter is under hardware control

controlled by the Count control.

Bit CM3 controls whether the counter counts in

Binary or BCD fashion. Bit CM4 determines whether

the counter counts up or down. Bit CM5 determines

whether the counter counts once and disarms itself,

or will continue counting and reloading the counter

until commanded to disarm.

Bit CM6 determines the source from which the

counter will be reloaded. The actions of CM6 depend

on the gating control settings. If CM6 is cleared, the

counter reloads from the Load Register at TC. If CM6

is set, the counter may reload from either the Load or

the hold register depending on the gating mode. It

may alternate with the Load register or be controlled

from the gate to reload from the load or hold register.

Bit CM7 controls whether hardware retriggering of the

counter is enabled. Its actions depend on the settings

of CM5, CM6 and the gating controls.

If some type of gating is enabled and CM7 is cleared,

hardware retriggering is disabled. When CM7 is set,

hardware retriggering is enabled and the counter is

retriggered any time an active gate edge is received.

When retriggered the counter value is saved in the

Hold register and the counter reloaded from the Load

If no gating is enabled and CM7 is cleared, the gate

input has no effect on counting. If CM7 is set then the

Gate input controls whether the counter is reloaded

from the Load or Hold Register.

Count Source (Bits CM8-12)

The count source determines which source is used

as an input to the counter. There are 20 possible

count sources, 16 of which may be selected with bits

CM8-12. Additional Count sources may be specified

with the extended registers. Figure 8 illustrates the

internal 24 bit prescaler whose outputs may be used

as count sources.

Gating Control (Bits CM13-15)

Gating control determines whether the counter is

hardware gated or not. When gating is disabled the

counter will continue as long as the counter is armed.

If any gating mode is enabled the counter action is

determined by some hardware gate condition.

Gating of the counter may be controlled from the gate

line associated with the counter or gate lines

associated with adjacent counters. Gating on the line

associated with the counter may be programmed for

edge or level sensitive, active high or active low. The

counter may also be gated by the TC output of the

previous counter. The gating control logic is outlined

in Figure 7.

COUNTER MODES

Counter modes continue as in the ‘9513 to retain

their mode designations A-X, with modes M, P, T, U

and V reserved. Tables 11-12 summarize the counter

modes and the associated settings of the counter

mode bits CM5-7 and CM13-15.

Figures 10 through 28 illustrate the counter modes.

All representative waveforms assume counting down

on rising source edges. A TC mode and Toggled

output waveform are shown in each waveform. For

waveforms which disarm automatically on TC the

software ARM command is shown in conjunction with

C7 C6 C5 C4 C3 C2 C1 C0

Command Register Bit

S5 S4 S3 S2 S1 S1-5 - Counter Group Select

S5 S4 S3 S2 S1 Arm Selected Counters

S5 S4 S3 S2 S1 Load Selected Counters

S5 S4 S3 S2 S1 Load and Arm Selected Counters

S5 S4 S3 S2 S1 Disarm and Save Selected Counters

S5 S4 S3 S2 S1 Save selected counters to Hold Registers

S5 S4 S3 S2 S1 Disarm Selected Counters

N4 N2 N1 N1-4 Counter Group Select (001 = N =

101

N4 N2 N1 Clear Selected Counter Toggle Out

N4 N2 N1 Set Selected Counter Toggle Out

N4 N2 N1 Step Selected Counter (up/down by CM3)

Table 5 - Counter Action Related Commands

C7 C6 C5 C4 C3 C2 C1 C0

Command Register Bit

Clear MM14 (Enable Data Pointer

Sequencing)

Clear MM12 (FOUT Gate On)

Clear MM13 (Enable 8 bit Bus Mode)

Set MM14 (Disable Data Pointer Sequencing)

Set MM12 (FOUT Gate Off)

Set MM13 (Enable 16 bit Bus Mode)

(Originally Reserved)

(Orig Reserved)

Enable Write Pre-Fetch

Disable Write Pre-Fetch

(Orig Reserved)

Master Reset

Table 6 - Device Level Commands

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