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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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CTS9513API-2 Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers |
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CTS9513API-2 Datasheet(HTML) 8 Page - List of Unclassifed Manufacturers |
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8 / 28 page  Celeritous Technical Services Corp 800.687.6510 / 806.793.0708 3308 34th St FAX 806.793.0710 Lubbock, Texas 79410 http://www.celeritous.com SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Copyright 2000 Celeritous Technical Services Corp 8 Rev E Tuesday, September 25, CTS9513-2 5 Chan 16 bit 20MHz Counter/Timer Data Pointer Sequencing (Bit MM14) When cleared, this bit enables automatic sequencing of the data pointer as defined by the data pointer commands. When set, the data pointer contents may only be changed by command. Scaling (Bit MM15) This bit determines whether the internal frequency prescaler operates as a BCD or Binary Divider. Figure 6 illustrates the internal 16 bit prescaler and its outputs. COUNTER REGISTERS Load Register The load register is a read/write counter register used to store the counter initial value. The load register value can be transferred into the counter each time the counter reaches a “terminal count.” A “terminal count” is defined as that period of time the counter value would have been zero if an external value had not been transferred into the counter. In all operating modes the value in either the load or hold register is transferred into the counter when the counter reaches terminal count. Hold Register The hold register is a read /write dual purpose register. In some operating modes the hold register may be used to store counter instantaneous values on command without disturbing the counter action for readout by the host. Other operating modes allow the hold register to be used as storage for counter values in a fashion similar to the Load register. The counter may be loaded from the Hold register at terminal count, or alternately loaded from the Load and Hold register at terminal count. Alarm Register Counters 1 and 2 contain an additional 16 bit Alarm register and corresponding 16 bit comparator. When the value in the counter matches the value stored in the Alarm register the output pin for the counter goes true. The output remains true as long as the counter value matches the Alarm register value. The output may be programmed for active high or active low by the counter mode register. COUNTER MODE REGISTER Each counter group contains a mode control register which controls the counter behavior, gating and output active states and polarities and counter source. The counter mode register is initialized at power-up to all zeroes. This translates to an initial counter mode of: 1 Output Low impedance to Ground 2 Count Down 3 Count Binary 4 Count Once 5 Load Register Selected C7 C6 C5 C4 C3 C2 C1 C0 Command Register Bit 0 0 0 E2 E1 G4 G2 G1 Load Data Pointer Commands G1-4 Group Pointer E1-2 Element Pointer 0 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 0 0 1 Counter 1 Mode Register 0 0 0 0 0 0 1 0 Counter 2 Mode Register 0 0 0 0 0 0 1 1 Counter 3 Mode Register 0 0 0 0 0 1 0 0 Counter 4 Mode Register 0 0 0 0 0 1 0 1 Counter 5 Mode Register 0 0 0 0 0 1 1 0 Reserved 0 0 0 0 0 1 1 1 Alarm Register 1 / Control Cycle 0 0 0 0 1 0 0 0 Reserved 0 0 0 0 1 0 0 1 Counter 1 Load Register 0 0 0 0 1 0 1 0 Counter 2 Load Register 0 0 0 0 1 0 1 1 Counter 3 Load Register 0 0 0 0 1 1 0 0 Counter 4 Load Register 0 0 0 0 1 1 0 1 Counter 5 Load Register 0 0 0 0 1 1 1 0 Reserved 0 0 0 0 1 1 1 1 Alarm Register 2 / Control Cycle 0 0 0 1 0 0 0 0 Reserved 0 0 0 1 0 0 0 1 Counter 1 Hold Register 0 0 0 1 0 0 1 0 Counter 2 Hold Register 0 0 0 1 0 0 1 1 Counter 3 Hold Register 0 0 0 1 0 1 0 0 Counter 4 Hold Register 0 0 0 1 0 1 0 1 Counter 5 Hold Register 0 0 0 1 0 1 1 0 Reserved 0 0 0 1 0 1 1 1 Master Mode Register / Control Cycle 0 0 0 1 1 0 0 0 Reserved 0 0 0 1 1 0 0 1 Hold Register Cycle 0 0 0 1 1 0 1 0 Hold Register Cycle 0 0 0 1 1 0 1 1 Hold Register Cycle 0 0 0 1 1 1 0 0 Hold Register Cycle 0 0 0 1 1 1 0 1 Hold Register Cycle 0 0 0 1 1 1 1 0 Reserved 0 0 0 1 1 1 1 1 Status Register Table 4 - CTS9513 Data Pointer Commands 6 No Retriggering 7 F1 source selected 8 Positive-true input polarity 9 No Gating The Counter Mode Register must be loaded while the counter is disarmed.. Table 10 summarizes the Counter Mode Register bit assignments. Output Control (Bits CM0-2) The counter output may be configured to be disabled, programmed to follow the counter terminal count or to toggle its state at each terminal count. The output logic for each counter is shown in Figure 8. The output may be disabled by either placing it in a high impedance state or in a low impedance state to ground. The outputs may also be hardware inhibited with the line. In the Terminal count mode, the output may be programmed to output an active high or active low pulse which is equal to one count source clock period. In the output toggle mode, the output changes state whenever the counter reaches a terminal count. The output state may be initialized with the SET and CLEAR counter commands. |
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