CTS9513API-2 datasheet(6/28 Pages) ETC

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Celeritous Technical Services Corp

800.687.6510 / 806.793.0708

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FAX

806.793.0710

Lubbock, Texas 79410

http://www.celeritous.com

SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE

Rev E

Tuesday, September 25,

CTS9513-2

5 Chan 16 bit 20MHz Counter/Timer

Figure 4 - CTS9513 Counter Block Diagram

DISARM Command

The DISARM command halts and disables any

further counting regardless of any hardware gating or

triggering. While DISARMed a counter may be

reloaded, SAVEd or incremented or decremented

using the STEP Command

LOAD Command

The LOAD command is used to load the counter with

the value stored in either the associated Load or Hold

of the counter once the counter is loaded.

SAVE Command

The SAVE command is used to save the contents of

the counter while counting continues. This allows the

counter value to be read without interfering with the

counter. Subsequent SAVE commands will overwrite

any previous contents of the Hold register.

CLEAR Command

The CLEAR command is used to reset the counter

output toggle to initialize it to a low state. This

command is only active if the output toggle is

programmed. It is inactive if a Terminal Count output

is specified.

SET Command

The SET command is used to set the counter output

toggle to initialize it to a high state. This command is

only active if the output toggle is programmed. It is

inactive if a Terminal Count output is specified.

STEP Command

The STEP Command increments of decrements the

selected counter by one depending on the operating

mode.

Master Mode Commands

A number of commands directly affect the Master

Mode Register without having to write to it directly.

These commands affect primarily the modes of the

data path, data pointer sequencing, enabling the

divided FOUT output clocks and clearing of latched

interrupt outputs from the counters.

Table 6

summarizes these commands.

STATUS REGISTER

The 16 bit Status Register indicates the

Status of the internal word pointer

Status of the counter outputs

Status of the counter interrupt outputs

When reporting the status of the counter output, the

status bit reflects the exact state of the output pin,

regardless of how the output pin state or toggle is

programmed.

Table 3 - CTS9513 Bus Control Line States

C/D

High Impedance

Read Data

Read Command

Write Data

Write Command

Illegal

COUNTER 1

COUNTER 2

COUNTER 3

COUNTER 4

COUNTER 5

SOURCE 1-5

GATE

1-5

INT

OUT

INT

OUT

INT

OUT

INT

OUT

INT

OUT

OSC

MUX

FOUT

CLK

16 BIT MASTER

MODE REGISTER

BUFFER

D0-D7

D8-D15

BUS

MUX

16 BIT COMMAND

BUS CONTROL

8 BIT DIVIDER

16 BIT STATUS

BIT

PRESCALER

16 bit

C/D

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