AM41DL6408H datasheet(37/66 Pages) AMD

No. de pieza	AM41DL6408H

Descripción Electrónicos	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

PDF	66 Pages

Scroll/Zoom	100%

Fabricante Electrónico	AMD [Advanced Micro Devices]

Página de inicio	http://www.amd.com

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37 / 66 page

November 24, 2003

Am41DL6408H

ADV ANCE

I N FO RMAT I O N

Table 15.

Write Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

Status

DQ7

(Note 2)

DQ6

DQ5

(Note 1)

DQ3

DQ2

(Note 2)

RY/BY#

Standard

Mode

Embedded Program Algorithm

DQ7#

Toggle

N/A

No toggle

Embedded Erase Algorithm

Toggle

Erase

Suspend

Mode

Erase-Suspend-

Read

Erase

Suspended Sector

No toggle

N/A

Toggle

Non-Erase

Suspended Sector

Data

Erase-Suspend-Program

DQ7#

Toggle

N/A

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