AM41DL6408H datasheet(59/66 Pages) AMD

No. de pieza	AM41DL6408H

Descripción Electrónicos	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

PDF	66 Pages

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Fabricante Electrónico	AMD [Advanced Micro Devices]

Página de inicio	http://www.amd.com

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59 / 66 page

November 24, 2003

Am41DL6408H

ADV ANCE

I N FO RMAT I O N

AC CHARACTERISTICS

Notes:

1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing.

2. t

CW is measured from CE1#s going low to the end of write.

3. t

WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.

4. t

AS is measured from the address valid to the beginning of write.

5. A write occurs during the overlap (t

WP) of low CE1#s and low WE#. A write begins when CE1#s goes low and WE# goes low when

asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A

write ends at the earliest transition when CE1#s goes high and WE# goes high. The t

WP is measured from the beginning of write

to the end of write.

Figure 32.

SRAM Write Cycle—CE1#s Control

Address

Data Valid

UB#s, LB#s

WE#

Data In

Data Out

High-Z

tWC

CE1#s

CE2s

tAW

tAS (See Note 2 )

tBW

tCW

(See Note 3)

tWR (See Note 4)

tWP

(See Note 5)

tDW

tDH

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