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AM41DL6408H Datasheet(PDF) 56 Page - Advanced Micro Devices |
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AM41DL6408H Datasheet(HTML) 56 Page - Advanced Micro Devices |
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56 / 66 page ![]() 54 Am41DL6408H November 24, 2003 ADV ANCE I N FO RMAT I O N AC CHARACTERISTICS SRAM Read Cycle Note: CE1#s = OE# = V IL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL Figure 29. SRAM Read Cycle—Address Controlled Parameter Symbol Description Speed Unit 71 70 85 t RC Read Cycle Time Min 55 70 85 ns t AA Address Access Time Max 55 70 85 ns t CO1, tCO2 Chip Enable to Output Max 55 70 85 ns t OE Output Enable Access Time Max 25 35 45 ns t BA LB#s, UB#s to Access Time Max 55 70 85 ns t LZ1, tLZ2 Chip Enable (CE1#s Low and CE2s High) to Low-Z Output Min 10 ns t BLZ UB#, LB# Enable to Low-Z Output Min 10 ns t OLZ Output Enable to Low-Z Output Min 5 ns t HZ1, tHZ2 Chip Disable to High-Z Output Max 20 25 ns t BHZ UB#s, LB#s Disable to High-Z Output Max 20 25 ns t OHZ Output Disable to High-Z Output Max 20 25 ns t OH Output Data Hold from Address Change Min 10 ns Address Data Out Previous Data Valid Data Valid tAA tRC tOH |
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