ST10F272M datasheet(76/175 Pages) STMICROELECTRONICS

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Watchdog timer

ST10F272M

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Watchdog timer

The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from

malfunctioning for long periods of time.

The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in

the time interval until the EINIT (end of initialization) instruction has been executed.

Therefore, the chip start-up procedure is always monitored. The software must be designed

to service the watchdog timer before it overflows. If, due to hardware or software related

failures, the software fails to do so, the watchdog timer overflows and generates an internal

hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components

to be reset.

Each of the different reset sources is indicated in the WDTCON register:

●

Watchdog Timer Reset in case of an overflow

●

Software Reset in case of execution of the SRST instruction

●

Short, Long and Power-On Reset in case of hardware reset (and depending of reset

pulse duration and RPD pin configuration)

The indicated bits are cleared with the EINIT instruction. The source of the reset can be

identified during the initialization phase.

The Watchdog Timer is 16-bit, clocked with the system clock divided by 2 or 128. The high

byte of the watchdog timer register can be set to a prespecified reload value (stored in

WDTREL).

Each time it is serviced by the application software, the high byte of the watchdog timer is

reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced

Table 40 shows the watchdog time range for 40 MHz CPU clock.

Table 40.

WDTREL reload value (fCPU = 40 MHz)

Reload value in WDTREL

Prescaler for fCPU = 40 MHz

2 (WDTIN = ‘0’)

128 (WDTIN = ‘1’)

FFh

12.8

µs

819.2µs

00h

3.277ms

209.7ms

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