ST10F272M datasheet(51/175 Pages) STMICROELECTRONICS

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ST10F272M

Interrupt system

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Interrupt system

The interrupt response time for internal program execution is from 125ns to 300ns at

40 MHz CPU clock.

The ST10F272M architecture supports several mechanisms for fast and flexible response to

service requests that can be generated from various sources (internal or external) to the

microcontroller. Any of these interrupt requests can be serviced by the Interrupt Controller or

by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is

suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’

from the current CPU activity to perform a PEC service. A PEC service implies a single Byte

or Word data transfer between any two memory locations with an additional increment of

either the PEC source or destination pointer. An individual PEC transfer counter is implicitly

decremented for each PEC service except when performing in the continuous transfer

mode. When this counter reaches zero, a standard interrupt is performed to the

corresponding source related vector location. PEC services are very well suited to perform

the transmission or the reception of blocks of data. The ST10F272M has eight PEC

channels, each of them offers such fast interrupt-driven data transfer capabilities.

An interrupt control register which contains an interrupt request flag, an interrupt enable flag

and an interrupt priority bit-field is dedicated to each existing interrupt source. Thanks to its

related register, each source can be programmed to one of sixteen interrupt priority levels.

Once starting to be processed by the CPU, an interrupt service can only be interrupted by a

higher prioritized service request. For the standard interrupt processing, each of the

possible interrupt sources has a dedicated vector location.

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an

individual trap (interrupt) number.

Fast external interrupt inputs are provided to service external interrupts with high precision

requirements. These fast interrupt inputs feature programmable edge detection (rising edge,

falling edge or both edges).

Fast external interrupts may also have interrupt sources selected from other peripherals; for

example, the CANx controller receives signals (CANx_RxD) and I2C serial clock signal can

be used to interrupt the system.

Table 29 shows all the available ST10F272M interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Table 29.

Interrupt sources

Source of interrupt or

PEC service request

Request

flag

Enable

flag

Interrupt

vector

Vector

location

Trap

number

CAPCOM Register 0

CC0IR

CC0IE

CC0INT

00’0040h

10h

CAPCOM Register 1

CC1IR

CC1IE

CC1INT

00’0044h

11h

CAPCOM Register 2

CC2IR

CC2IE

CC2INT

00’0048h

12h

CAPCOM Register 3

CC3IR

CC3IE

CC3INT

00’004Ch

13h

CAPCOM Register 4

CC4IR

CC4IE

CC4INT

00’0050h

14h

CAPCOM Register 5

CC5IR

CC5IE

CC5INT

00’0054h

15h

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