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ZIOL2201 Datasheet(PDF) 35 Page - Renesas Technology Corp |
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ZIOL2201 Datasheet(HTML) 35 Page - Renesas Technology Corp |
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35 / 92 page ![]() ZIOL2xxx Datasheet © 2016 Integrated Device Technology, Inc. 35 April 26, 2016 As regards the access type to a particular register the following four types have been implemented: 1. r/w normal read/write 1 2. r read only 3. r/rst read only, clear by read 4. w/pulse writing to such type of registers causes a partial reset of certain IC functions which correspond to the assigned bit of the write accessed register; reading is possible but will return no useful information In order to illustrate for instance the w/pulse type a write access to status register MON_RST_LOCK_WURQ shall be explained. The bits of this register are assigned to • the power fail event (bit 4) and • the IO-Link specific wake-up request event (bit 3) and • the COM/AUX driver over-current event (bit 2 and 1) and • the over-temperature event (bit 0). Writing the value 0x08 (MON_RST_WURQ = 1) to the register would cause a reset of the previously detected and stored wake-up request. In doing so the to the IC interconnected µC acknowledges the occurred wake-up request thus the IC is ready to detect the next wake-up request. Table 3.7 Register Table Reg.-Name Addr. Bit-Field Bit Reset- Value r/w Comment Reference CONFIGURATION REGISTER IRQ_ENABLE 0 7:0 255 r/w Figure 3.14 0 IRQ_EN_POWER_FAIL 7 1 r/w Power fail interrupt enable Added in Rev B 0 IRQ_EN_WURQ 6 1 r/w WURQ interrupt enable 0 IRQ_EN_VALID_FLAG_ERR 5 1 r/w Valid-flag error interrupt enable 0 IRQ_EN_EEPROM_ERR 4 1 r/w Single bit error interrupt enable 0 IRQ_EN_EEPROM2_ERR 3 1 r/w Multiple bit error interrupt enable 0 IRQ_EN_LOCK_AUX 2 1 r/w interrupt enable for over-load lock of AUX line driver 1 Note: IC versions ZIOL2xx2 do not allow any write access. |
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