ZIOL2201 datasheet(11/92 Pages) RENESAS

11 / 92 page

ZIOL2xxx Datasheet

April 26, 2016

Symbol

Parameter

Min

Typ

Max

Unit

Conditions

Microcontroller Interface

VLIH

Voltage range for input ”high”

level

2.5

5.5

@ VDD_LV = 3.6V, otherwise

VLIH-min = 0.7 ∗ VDD_LV

VLIL

Voltage range for input ”low” level

-0.3

0.9

@ VDD_LV = 3.0V, otherwise

VLIL-max = 0.3 ∗ VDD_LV

ILIH

Logic “high”

input current

@ pins without

pull-up/pull-down

resistors:

INT_L, WURQ_L

-1

µA

@ VLIH = VDD_LV

ILIL

Logic “low”

input current

-1

µA

@ VLIL = 0V

ILIH_PD

Logic “high”

input current

@ pins with pull-

down resistors:

TX_EN/SPI_CLK,

TX/MOSI,

AUX_EN,

AUX_TX,

DC_RDY

-300

-150

µA

@ VLIH = VDD_LV-max = 3.6V

@ VLIH = 5.5V, VDD_LV-max = 3.6V

ILIL_PD

Logic “low”

input current

-1

µA

@ VLIL = 0V, VDD_LV-max = 3.6V

@ VLIL = 0V, VDD_LV-max = 3.0V

ILIH_PU

Logic “high”

input current

@ pins with pull-

up resistors:

RST_L,

SPI_EN_L

-1

µA

@ VLIH-min = VDD_LV-max = 3.0V

@ VLIH-max = VDD_LV-max = 3.6V

ILIL_PU

Logic “low”

input current

-150

250

µA

@ VLIL = 0V, VDD_LV-max = 3.6V

@ VLIL = -0.3V, VDD_LV-max = 3.6V

VLOL

Logic “high”

output voltage

@ output pins:

RX/MISO,

AUX_RX

∗V

DD_LV

@ ILIL = 1mA

VLOH

Logic “high”

output voltage

100

∗V

DD_LV

@ ILIH = -1mA

Internal Current Consumption

10)

IVDD

Current into VDD

1.7

2.5

SPI_EN=3.3V

ILR_IN

Current into LR_IN

2.2

3.4

SPI_EN=3.3V

The mentioned typical values of IC properties are provided for information only and shall not be considered as statistical

guaranteed mean values. Typical values are not subject for measurement while the electrical test of each IC – they are correct by

design.

If the output current exceeds the configured current limit, the IC will raise an overload signal which causes up-counting of the

overload counter (if configured) and which definitely limits the output current. However, the current limit will be performed after a

certain settling time in order to ensure the configured slope of the output signal.

Absolute edge rise and fall times are proportional to VDD_HV

A minimum of the output current must be provided by the application circuit. Otherwise the DC/DC converter shall be unused by

interconnecting the FB pin with the LR_OUT pin. The required voltage divider (refer to Figure 3.21) may provide this current partly

or in full.

Slew-rate measured after settlement time of the output signal

Configurable with an external voltage divider (refer to chapter 3.5)

The ripple on the output voltage depends significantly on both the external components and the PCB layout. Reference PCB

layouts are available from IDT. The layouts used in the application kits are shown in Figure 4.4; detailed layout data of the

application kits are available from IDT upon request.

The efficiency of the DC/DC converter is depending on the external components and the used PCB layout. Moreover, there is an

influence from several operational conditions which is illustrated in the diagram of Figure 2.2

Microcontroller interface pins are : RST_L, SPI_EN_L, INT_L, WURQ_L, TX_EN/SPI_CLK, TX/MOSI, RX/MISO, AUX_EN,

AUX_TX, AUX_RX, DC_RDY

10)

Current consumption is measured by applying the maximum supply voltage at the supply pins VDD and LR_IN (VVDD_HV=36V,

Vin=36V) and using a decoupling cap of 10µF between LR_OUT and ground. Both VDD and both VSS pins are interconnected,

respectively. Pins TX_EN/SPI_CLK, AUX_TX, TX_EN, AUX_EN, PFD, COM_I, AUX_I are connected to ground.

ZIOL2201 Datasheet(PDF) 11 Page - Renesas Technology Corp

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