www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61

Revision 1.01

7 - 29

AS1160/AS1161

Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s

Deserializer Electrical Characteristics

Figure 21 on page 13

0ns

4

ns

DO+, DO- High-to-

Tri-State Delay

Figure 22 on page 14

2

1.5

5

ns

DO+, DO- Low-to-

Tri-State Delay

1.5

5

ns

DO+, DO- Tri-State-to-

High Delay

1.5

5

ns

DO+, DO- Tri-State-to-

Low Delay

1.5

5

ns

PWDNN minimum low time

Figure 23 on page 14

50

µs

SYNC Pulse Width

Figure 25 on page 15

5 x

ns

Serializer PLL Lock Time

Figure 24 on page 14

400 x

ns

Serializer Delay

Figure 26 on page 15

+ 3

+ 5

ns

Deterministic Jitter (p-p)

(Worst Case) ICC-Pattern

Figure 32 on page 18

f = 20MHz

150

300

ps

(pp)

f = 66MHz

50

100

ps

(pp)

Random Jitter

(Worst Case) ICC-Pattern

f = 20MHz

25

45

ps

(RMS)

f = 66MHz

8

15

1. Guaranteed by simulation and characterization.

2. Because the serializer is in tri-state mode, the deserializer will lose PLL lock and have to resynchronize before

data transfer.

Table 7. Electrical Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Deserializer Bus LVDS DC Specifications (pins RI+ and RI-)

Differential Threshold High

Voltage

+10

+75

mv

Differential Threshold Low

Voltage

-75

-20

Input Current

-1

+1

µA

-1

+1

Deserializer LVCMOS/LVTTL DC Specifications (input pins PWDNN, RCKR/FN, REN, REFCLK; output pins

ROUT0:ROUT9, RCLK, LOCKN)

High Level Input Voltage

2.0

V

Low Level Input Voltage

GND

0.8

V

Input Current

-1

+1

µA

Table 6. Serializer Switching Characteristics

1

Symbol

Parameter

Conditions

Min

Typ

Max

Unit