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AS1160/AS1161

Datasheet - D e t a i l e d D e s c r i p t i o n

10 Detailed Description

The serializer/deserializer chipset transfers 10 parallel LVTTL data bits over a serial Bus LVDS link up to 660Mbps at

clock speeds from 20MHz to 66MHz.

For the serializer, an on-board PLL serializes the input data and inserts two control bits (start & stop bit) into the data

stream.

The deserializer uses a separate reference clock (REFCLK) and an onboard PLL to extract the clock information from

the incoming data stream and then deserialize the data. The deserializer monitors the incoming clock information,

determines lock status and asserts the LOCKN output high when loss of lock occurs.

Note: The chipset is also capable of driving data over unshielded twisted pair cable.

The chipset has three active states of operation:

- Initialization

- Data Transfer

- Resynchronization

The chipset also has two passive states:

- Powerdown

- Tri-State

Note: There are also test modes for JTAG access and at-speed BIST (built-in-self-test).

Initialization

Initialization of both devices must occur before data transmission begins. Initialization refers to synchronization of the

serializer and deserializer PLLs to local clocks, which may be the same or separate. Afterwards, synchronization of the

deserializer to the serializer occurs.

to stay low for at least 50µs to ensure proper operation (see Figure 23 on page 14), the respective output enter

tri-state. After PWDNN is high the PLL in the serializer begins locking to a local clock.

clock. For the serializer, the local clock is the transmited clock (TCLK) provided by the source ASIC or other

device. For the deserializer, a local clock must be applied to pin REFCLK that can be provided by any source.

The serializer outputs remain in tri-state while the PLL locks to the TCLK. After locking to TCLK, the serializer

is now ready to send data or SYNCPATs (SYNC patterns), depending on the levels of the SYNC1 and SYNC2

inputs or a data stream.

The SYNCPAT sent by the serializer consists of six ones and six zeros switching at the input clock rate. Note

that the deserializer LOCKN output will remain high while its PLL locks to the incoming data or to SYNCPATs

on the input.

2. The deserializer PLL must synchronize to the serializer to complete initialization. The deserializer will lock to

non-repetitive data patterns. However, the transmission of SYNCPATs enables the deserializer to lock to the

serializer signal within a specified time (see Figure 24 on page 14).

The application determines control of pins SYNC1 and SYNC2. A direct feedback loop from the LOCKN pin is

mandatory (see Figure 36 on page 23). In all cases the serializer stops sending SYNCPATs after both SYNC

inputs return low.

When the deserializer detects edge transitions at the bus LVDS input, it will attempt to lock to the embedded

clock information. When the deserializer locks to the bus LVDS clock, the LOCKN output will go low. When

LOCKN is low, the deserializer outputs represent incoming bus LVDS data.