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AS1160 Datasheet(PDF) 22 Page - ams AG |
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AS1160 Datasheet(HTML) 22 Page - ams AG |
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22 / 29 page ![]() www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Revision 1.01 22 - 29 AS1160/AS1161 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 11 Application Information Power Considerations An all CMOS design of the serializer and deserializer makes them inherently low power devices. In addition, the con- stant current source nature of the bus LVDS outputs minimizes the slope of the speed vs. IDD curve of conventional CMOS designs. The pins AVDD and DVDD should be bypassed with a 100nF and a 1nF ceramic capacitor in parallel. The 1nF capac- itor should be closest to the pin. Powering up the Deserializer The AS1161 can be powered up at any time by following a proper sequence. The REFCLK input can be running before the deserializer powers up and it must be running in order for the deserializer to lock to incoming data. The deserializer outputs will remain in tri-state until the deserializer detects data transmission at its inputs and locks to the incoming data stream. Transmitting Data Once the serializer (AS1160) and deserializer (AS1161) are powered up, they must be phase locked to each other to transmit data. Phase locking occurs when the deserializer locks to incoming data or when the serializer sends patterns. The serializer sends SYNCPATs whenever the SYNC1 or SYNC2 inputs are high. The LOCKN output of the deserial- izer remains high until it has locked to the incoming data stream. Connecting the LOCKN output of the deserializer to one of the SYNC inputs of the serializer will guarantee that enough SYNCPATs are sent to achieve deserializer lock (see Figure 36 on page 23). As long as the deserializer LOCKN output is low, valid data is presented at the deserializer outputs (ROUT0:ROUT9), except for the specific case of loss of lock during transmission (see Lock Loss Recovery on page 23). Table 11. Deserializer Truth Table Inputs Outputs PWDNN REN LOCKN ROUTx RCLK High High High (not locked) Z Z High High Low (not locked) Active 1 1. Active indicates the RCLK will be running if the deserializer is locked. The timing of RCLK with respect to ROUT0:ROUT9 is determined by RCKR/FN. ROUT0:ROUT9 and RCLK are tri-stated when LOCKN is asserted high. Active 1 Low X (dont care) Z Z Z High Low Active 2 2. Active indicates the LOCKN output will reflect the state of the deserializer with regard to the selected data stream. ZZ |
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