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AS1160 Datasheet(PDF) 4 Page - ams AG

No. de pieza AS1160
Descripción Electrónicos  20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer
PDF  29 Pages
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Fabricante Electrónico  AMSCO [ams AG]
Página de inicio  http://www.ams.com
Logo AMSCO - ams AG

AS1160 Datasheet(HTML) 4 Page - ams AG

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www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61
Revision 1.01
4 - 29
AS1160/AS1161
Datasheet - P i n o u t
Figure 3. AS1161 Pin Assignments (Top View)
Table 2. AS1161 Pin Descriptions
Pin Number
Pin Name
Description
See Figure 3
ROUT0:ROUT9 Data Output. ±4mA CMOS level outputs.
RCKR/FN
Recovered Clock Rising/Falling Strobe Select. LVTTL level input. Selects RCLK
active edge for strobing of ROUT0:ROUT9 data.
1 = Rising edge.
0 = Falling edge.
REFCLK
Reference Clock Input. LVTTL level input. Input for 20MHz - 66MHz system clock.
RI+
+ Serial Data Input. Non-inverting Bus LVDS differential input.
RI-
- Serial Data Input. Inverting Bus LVDS differential input.
PWDNN
Powerdown. LVTTL level input. Driving this pin low shuts down the PLL, tri-states
the outputs and puts the device into low power sleep mode.
LOCKN
Lock. CMOS level output. This signal goes low when the deserializer PLL locks onto
the embedded clock edge.
RCLK
Recovered Clock. CMOS level output. Parallel data rate clock recovered from
embedded clock. Used to strobe ROUT0:ROUT9.
REN
Output Enable. LVTTL level input. If REN is set to logic low ROUT0:ROUT9 and RCLK
are in tri-state condition.
DVDD
+3.0V to +3.6V Digital Circuit Power Supply. This is the supply for all digital
circuitry.
DGND
Digital Circuit Ground
AVDD
+3.0V to +3.6V Analog Power Supply (PLL and Analog Circuits). AVDD and DVDD
should be at the same potential and must not be more than 0.3V apart even on
transient basis. Both supplys should be decoupled by a capacitor of typically 10nF.
AGND
Analog Ground (PLL and Analog Circuits).
TDI
IEEE 1149.1 Test Data Input
TDO
IEEE 1149.1 Test Data Output
TMS
IEEE 1149.1 Test Mode Select Input
TCK
IEEE 1149.1 Test Clock Input
TRSTN
IEEE 1149.1 Test Reset Input
N/C
No Connection. Leave open-circuit, do not connect these pins.
A1
DGND
A2
N/C
A3
REFCLK
A4
AGND
A5
ROUT1
A6
DGND
A7
DVDD
B1
AVDD
B2
AGND
B3
RCKR/FN
B4
ROUT2
B5
DGND
B6
ROUT3
B7
DVDD
C1
RI-
C2
AVDD
C3
N/C
C4
ROUT0
C5
DVDD
C6
DVDD
C7
ROUT4
D1
REN
D2
RI+
D3
PWDNN
D4
N/C
D5
DVDD
D6
ROUT5
D7
DGND
E1
LOCKN
E2
RCLK
E3
N/C
E4
DGND
E5
TCK
E6
TRSTN
E7
DGND
F1
AVDD
F2
AVDD
F3
AGND
F4
AGND
F5
ROUT8
F6
TDI
F7
ROUT6
G1
AVDD
G2
AGND
G3
DGND
G4
ROUT9
G5
ROUT7
G6
TDO
G7
TMS



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