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AS1160 Datasheet(PDF) 1 Page - ams AG |
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AS1160 Datasheet(HTML) 1 Page - ams AG |
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1 / 29 page  AS1160/AS1161 20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LV DS Serializer/Deserializer www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61 Revision 1.01 1 - 29 Data sheet 1 General Description The AS1160 (serializer) is designed to convert 10-bit wide parallel LVCMOS/LVTTL data bus signals into a single high-speed LVDS serial data stream with clock. The AS1161 (deserializer) transforms the high-speed LVDS serial data stream back into a 10-bit wide parallel data bus with recovered parallel clock. Both devices are compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture (including the defined boundary-scan test logic and test access port consisting of Test Data Input, Test Data Out, and Test Mode Select, Test Clock, and Test Reset). The devices also feature an at-speed BIST mode which allows the interconnects between the serializer and deserializer to be verified at-speed. The single differential-pair data-path makes PCB design easier, and reduced cable/PCB-trace count and connec- tor size significantly reduce cost. Since one output trans- mits clock and data bits serially, clock-to-data and data- to-data skew are eliminated. Powerdown mode reduces supply current when both devices are idle. Both devices are available in a CTBGA 49-bumps pin package. Figure 1. Block Diagrams 2 Key Features ! Serial Bus LVDS Data Rate: 660 Mbps @ 66MHz Clock ! 10-bit Parallel Interface ! Synchronization Mode and Lock Indicator ! Programmable Edge Trigger on Clock ! High Impedance on Rx Inputs during Poweroff ! Bus LVDS Serial Output Load: 28 Ω ! IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode ! Clock Recovery from PLL Lock to Random Data Patterns ! Guaranteed Transition each Data Transfer Cycle ! Chipset (Tx + Rx) Power Consumption: < 500 mW @ 66MHz ! Single Differential-Pair eliminates Multi-Channel Skew ! Flow-Through Pinout for Simple PCB Layout ! Small CTBGA 49-bumps Package 3 Applications The devices are ideal for cellular phone base stations, add drop muxes, digital cross-connects. DSLAMs, net- workswitches and routers or backplane interconnect. AS1160 DO+ DO- TCLK TCKR/FN Input Latch PLL DIN0:9 Parallel- to-Serial 10 Timing & Control DEN SYNC1 SYNC2 TDI TDO TCK TMS IEEE 1149.1 Test Access Port TRSTN AS1161 RI+ RI- Output Latch PLL ROUT0:9 Parallel- to-Serial 10 Timing & Control REFCLK REN LOCKN RCLK Clock Recovery RCKR/FN LVDS TDI TDO TCK TMS IEEE 1149.1 Test Access Port TRSTN |
Número de pieza similar - AS1160 |
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Descripción similar - AS1160 |
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