www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61

Revision 1.01

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AS1160/AS1161

Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s

Scan Circuitry Timing Requirements

Note: All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or

SQC (Statistical Quality Control) methods.

RCLK Duty Cycle

45

50

55

ns

High to Tri-State Delay

Figure 29 on page 16

36

ns

Low to Tri-State Delay

36

ns

Tri-State to High Delay

46

ns

Tri-State to Low Delay

46

ns

2

Deserializer PLL Lock

Time from PWDNN

(with SYNCPAT)

Figure 30 on page 17,

Figure 31 on page 17

20MHz

5.2

7.5

µs

66MHz

1.8

3

µs

2

Deserializer PLL Lock

Time from SYNCPAT

20MHz

5.1

7.5

µs

66MHz

1.9

3

µs

Tri-State to High Delay

(Powerup)

LOCKN

4

12

ns

1

RCLK low time before

LOCK achieved

RCLK

ns

3

Deserializer Noise

Margin

Figure 33 on page 18

20MHz

0.8

1

ns

66MHz

200

300

ps

1. Guaranteed by simulation and characterization.

running and stable, and with specific conditions for the incoming data stream synchronization patterns (SYNC-

mode. SYNCPATs should be sent to the device before initiating either condition.

RI-) conditions change from not receiving data to receiving SYNCPATs.

before bit errors occur. The deserializer noise margin is guaranteed by design using statistical analysis.

Table 10. Scan Circuitry Timing Requirements

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TCK Clock Frequency

Figure 15 on page 12

25

MHz

TCK Clock Period

40

ns

TCK to TDI, TMS Setup Time

2.0

ns

TCK to TDI, TMS Hold Time

3.0

ns

TCK Pulse Width, High or Low

10.0

ns

TRSTN Pulse Width, Low

2.5

ns

TRSTN-to-TCK Recovery Time

2.0

ns

TCK to TDO Delay

10

ns

TCK to TDO High Z Delay

10

ns

Table 9. Deserializer Switching Characteristics

1

Symbol

Parameter

Conditions

Pin/

Frequency

Min

Typ

Max

Unit