AD9882SLASHPCB datasheet(11/36 Pages) AD

11 / 36 page

REV. A

AD9882

–11–

RED

Data Output, RED Channel

GREEN

Data Output, GREEN Channel

BLUE

Data Output, BLUE Channel

These are the main data outputs. Bit 7 is the MSB.

The delay from pixel sampling time to output is

fixed. When the sampling time is changed by

adjusting the PHASE register, the output timing

is shifted as well. The DATACK and HSOUT

outputs are also moved, so the timing relation-

ship among the signals is maintained.

Please refer to the timing diagrams for more

information.

POWER SUPPLY

Main Power Supply

These pins supply power to the main elements of

the circuit. They should be as quiet as possible.

VDD

Digital Output Power Supply

A large number of output pins (up to 25) switch-

ing at high speed (up to 140 MHz) generates a

lot of power supply transients. These supply

pins are identified separately from the VD pins

so special care can be taken to minimize out-

put noise transferred into the sensitive analog

circuitry.

If the AD9882 is interfacing with lower voltage

logic, VDD may be connected to a lower supply

voltage (as low as 2.2 V) for compatibility.

PVD

Clock Generator Power Supply

The most sensitive portion of the AD9882 is the

clock generation circuitry. These pins provide

power to the clock PLL and help the user design

for optimal performance. The designer should

provide noise-free power to these pins.

GND

Ground

The ground return for all circuitry on chip. It is

recommended that the AD9882 be assembled on

a single solid ground plane, with careful attention

to ground current paths.

Table III. Interface Selection Controls

Analog

Digital

AIO

Interface

AIS

Active

(0FH Bit 2)

Detect

(0FH Bit 1)

Interface

Description

XX0

Analog

Force the analog interface active.

1Digital

Force the digital interface active.

00X

None

Neither interface was detected. Both interfaces are

powered down.

01X

Digital

The digital interface was detected. Power down the

analog interface.

10X

Analog

The analog interface was detected. Power down the

digital interface.

110

Analog

Both interfaces were detected. The analog interface

gets priority.

1Digital

Both interfaces were detected. The digital interface

gets priority.

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