AD9882SLASHPCB datasheet(15/36 Pages) AD

15 / 36 page

REV. A

AD9882

–15–

1.0 V

0.5 V

0.0 V

GAIN

00H

FFH

OFFSET = 3FH

OFFSET

= 7FH

OFFSET

= 00H

OFFSET

3FH

OFFSET

= 00H

Figure 2. Gain and Offset Control

Sync-on-Green (SOG)

The Sync-on-Green input operates in two steps. First, it sets

abaseline clamp level off of the incoming video signal with a

negative peak detector. Second, it sets the Sync trigger level

(nominally 150 mV above the negative peak). The exact trigger

level is variable and can be programmed via Register 0FH,

Bits 7–3. The Sync-on-Green input must be ac-coupled to the

green analog input through its own capacitor as shown in Figure 3.

The value of the capacitor must be 1 nF

±20%. If Sync-on-Green

is not used, this connection is not required and SOGIN should

be left unconnected. (Note: The Sync-on-Green signal is always

negative polarity.) Please refer to the Sync Processing section

for further information.

47nF

RAIN

BAIN

GAIN

SOGIN

1nF

Figure 3. Typical Clamp Configuration

Clock Generation

A Phase Locked Loop (PLL) is employed to generate the pixel

clock. The Hsync input provides a reference frequency for the

PLL. A Voltage Controlled Oscillator (VCO) generates a much

higher pixel clock frequency. This pixel clock is divided by the

PLL divide value (Registers 01H and 02H) and phase compared

with the Hsync input. Any error is used to shift the VCO frequency

and maintain lock between the two signals.

The stability of this clock is a very important element in provid-

ing the clearest and most stable image. During each pixel time,

there is a period during which the signal is slewing from the old

pixel amplitude and settling at its new value. Then there is a

time when the input voltage is stable, before the signal must

slew to a new value (Figure 4). The ratio of the slewing time to

the stable time is a function of the bandwidth of the graphics

DAC and the bandwidth of the transmission system (cable and

termination). It is also a function of the overall pixel rate. Clearly,

if the dynamic characteristics of the system remain fixed, then

the slewing and settling time is likewise fixed. This time must be

subtracted from the total pixel period, leaving the stable period.

At higher pixel frequencies, the total cycle time is shorter, and

the stable pixel time becomes shorter as well.

PIXEL CLOCK

INVALID SAMPLE TIMES

Figure 4. Pixel Sampling Times

Any jitter in the clock reduces the precision with which the

sampling time can be determined and must also be subtracted

from the stable pixel time.

Considerable care has been taken in the design of the AD9882’s

clock generation circuit to minimize jitter. As indicated in Fig-

ure 5, the clock jitter of the AD9882 is less than 6% of the total

pixel time in all operating modes, making the reduction in the

valid sampling time due to jitter negligible.

135.0

25.1 31.5 36.0 40.0

85.5

50.0 56.2 65.0 75.0 78.7

94.5 108.0

PIXEL CLOCK FREQUENCY – MHz

Figure 5. Pixel Clock Jitter vs. Frequency

AD9882/PCB Datasheet(PDF) 15 Page - Analog Devices

AD9882/PCB Datasheet(HTML) 15 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Descarga

Enlace URL