AD9882SLASHPCB datasheet(30/36 Pages) AD

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AD9882

Active Interface

This bit is used to indicate which interface should be active, analog

or digital. It checks for activity on the analog interface and for

activity on the digital interface, then determines which should be

active according to Table XLI. Specifically, analog interface detec-

tion is determined by OR-ing Bits 7, 6, and 5 in this register. Digital

interface detection is determined by Bit 4 in this register. If both

interfaces are detected, the user can determine which has priority

via Bit 1 in Register 0FH. The user can override this function

via Bit 2 in Register 0FH. If the override bit is set to logic 1, then

this bit will be forced to the same state as Bit 1 in Register 0FH.

Table XLI. Active Interface Results

Bits 7, 6, or 5

Bit 4

(Analog

(Digital

Detection)

Override

Soft

Power-Down

(Seek Mode)

Bit 1 in 0FH

AI = 0 means analog interface

AI = 1 means digital interface

The override bit is in Register 0FH, Bit 2.

AHS

Active Hsync

This bit indicates which Hsync input source is being used by the

PLL (Hsync input or Sync-on-Green). Bits 6 and 7 in Register

15H determine which source is used. If both Hsync and SOG

are detected, the user can determine which has priority via Bit 3

in Register 10H. The user can override this function via Bit 4

in Register 10H. If the override bit is set to logic 1, then this

bit will be forced to the same state as Bit 3 in Register 10H.

Table XLII. Active Hsync Results

Hsync Detect SOG Detect

Override

AHS

Bit 7

Bit 6

Bit 4

Bit 7

0Bit 3 in 10H

Bit 3 in 10H

AHS = 0 means use the Hsync pin input for Hsync

AHS = 1 means use the SOG pin input for Hsync

The override bit is in Register 10H, Bit 4.

Detected Hsync Input Polarity Status

This bit reports the status of the Hsync input polarity detection

circuit. It can be used to determine the polarity of the Hsync

input. The detection circuit’s location is shown in the Sync

Processing Block Diagram, Figure 18.

Table XLIII. Detected Hsync Input Polarity Status

Hsync Polarity

Status

Result

0Hsync polarity is negative/active low.

1Hsync polarity is positive/active high.

AVS

Active Vsync

This bit indicates which Vsync source is being used for the analog

interface: the Vsync input or output from the sync separator.

If the override bit (10H, Bit 1) is set to logic 1, then this bit will be

forced to the same state as Bit 0 in Register 10H.

Table XLIV. Active Vsync Results

Vsync Detect

Override

Bit 5

Bit 1

AVS

000

101

Bit 0 in 10H

AVS = 0 means Vsync input

AVS = 1 means Sync separator

The override bit is in Register 10H, Bit 1.

Detected Vsync Output Polarity Status

This bit reports the status of the Vsync output polarity detection

circuit. It can be used to determine the polarity of the Vsync

output. The detection circuit’s location is shown in the Sync

Processing Block Diagram, Figure 18.

Table XLV. Detected Vsync Input Polarity Status

Vsync Polarity Status

Result

0Vsync polarity is active high.

1Vsync polarity is active low.

Detected Coast Polarity Status

This bit reports the status of the coast input polarity detection

circuit. The detection circuit’s location is shown in the Sync

Processing Block Diagram, Figure 18. This bit only applies to

the internal Coast and does not apply when Coast is disabled.

Table XLVI. Detected Coast Input Polarity Status

Hsync Polarity

Status

Result

0Coast polarity is negative/active low.

1Coast polarity is positive/active high.

Key Read Verification

This bit reports wherever HDCP keys are detected.

Table XLVII. Key Read Verification

Detect

Function

0Not detected

1Detected

MDA and MCL Three-State

The MDA and MCL three-state feature allows the EEPROM to

be programmed in-circuit. The MDA/MCL port must be three-

stated before attempting to program the EEPROM using an

external master. The keys will be stored in an I

2C compatible

3.3 V serial EEPROM of at least 512 bytes. The EEPROM

should have a device address of A0H.

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