CS89712 datasheet(55/170 Pages) CIRRUS

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CS89712

DS502PP2

the Collision Detection circuit informs the MAC by

asserting the internal Collision signal (see Section

2.26, “Media Access Control Engine” for collision

handling).

2.29 Basic Transmit Operation

Transmit operations occur in the following order

(using interrupts):

1) Software bids for storage of the frame by writ-

ing the Transmit Command to the TxCMD Port

and the transmit frame length to the TxLength

Port.

2) Software reads the BusST register to see if the

Rdy4TxNOW bit (Bit 8) is set. To read the

BusST register, the software must first set the

Ethernet Port Pointer at the correct location by

writing 0138h to the Ethernet Port Pointer Port

(offset address 000Ah). It can then read the

BusST register from the Ethernet Port Data

Port (offset address 000Ch). If Rdy4TxNOW is

set, the frame can be written. If clear, the soft-

ware must wait for Ethernet port buffer memo-

ry to become available. If Rdy4TxiE (bit 8 of

BufCFG) is set, an interrupt is generated when

Rdy4Tx (bit 8 of BufEvent) becomes set. If the

TxBidErr bit (BusST register bit 7) is set, the

transmit length is not valid.

3) Once the Ethernet port is ready to accept the

frame, software executes repetitive write in-

structions (REP OUT) to the Receive/Transmit

Data Port to transfer the entire frame from host

RAM to the Ethernet port’s memory.

For a more detailed description of transmit, see

Section 2.34, “Transmit Operation”.

2.30 Basic Receive Operation

Receive operations occur in the following order (in

this example, interrupts are enabled to signal the

presence of a valid receive frame):

1) A frame is received by the CS89712, triggering

an enabled interrupt.

2) The software reads the Interrupt Status Queue

Port and is informed of the receive frame.

3) The software reads the frame data by executing

repetitive read instructions from the Re-

ceive/Transmit Data Port to transfer the frame

from Ethernet port memory to host RAM. Pre-

ceding the frame data are the contents of the

RxStatus register and the RxLength register.

For a more detailed description of receive, see Sec-

tion 2.32, “Basic Receive Operation”.

2.31 Managing Interrupts & Status Queue

The Interrupt Status Queue (ISQ) is used by the

Ethernet port to communicate Event reports.

Whenever an event occurs that triggers an enabled

interrupt, the Ethernet port sets the appropriate

bit(s) in one of five registers, maps the contents of

that register to the ISQ, and drives the selected in-

terrupt request pin high (if an earlier interrupt is

waiting in the queue, the interrupt request pin will

already be high). When the software services the

interrupt, it must first read the ISQ to learn the na-

ture of the interrupt. It can then process the inter-

rupt (the first read to the ISQ causes the interrupt

request pin to go low.)

Three of the registers mapped to the ISQ are event

registers: RxEvent, TxEvent, and BufEvent. The

other two registers are counter-overflow reports:

RxMISS and TxCOL. There may be more than one

RxEvent report and/or more than one TxEvent re-

port in the ISQ at a time. However, there may be

only one BufEvent report, one RxMISS report and

one TxCOL report in the ISQ at a time.

Event reports stored in the ISQ are read out in the

order of priority, with RxEvent first, followed by

TxEvent, BufEvent, RxMiss, and then TxCOL.

The software only needs to read from one location

to get the interrupt currently at the front of the

queue. It is located at offset address 0008h. Each

time the software reads the ISQ, the bits in the cor-

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