CS89712 datasheet(86/170 Pages) CIRRUS

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CS89712

DS502PP2

3.5.4

SYSFLG1 — The System Status Flags Register (address 0x8000.0140)

The system status flags register is a 32-bit read only register, which indicates various system information. The bits

in the system status flags register SYSFLG1 are defined in Table 40.

31:30

29282726

VERID

BOOTBIT1

BOOTBIT0

SSIBUSY

21:16

CTXFF

CRXFE

UTXFF1

URXFE1

RTCDIV

CLDFLG

PFFLG

RSTFLG

NBFLG

UBUSY1

7:4

DID

WUON

WUDR

DCDET

MCDR

Bit

Description

MCDR: Media changed direct read. This bit reflects the INVERTED non-latched status of the

media changed input.

DCDET: This bit will be set if a non-battery operated power supply is powering the system (it is

the inverted state of the nEXTPWR input pin).

WUDR: Wake up direct read. This bit reflects the non-latched state of the wakeup signal.

WUON: This bit will be set if the system has been brought out of the Standby State by a rising

edge on the wakeup signal. It is cleared by a system reset or by writing to the HALT or STDBY

locations.

4:7

DID: Display ID nibble. This 4-bit nibble reflects the latched state of the four LCD data lines. The

state of the four LCD data lines is latched by the LCDEN bit, and so it will always reflect the last

state of these lines before the LCD controller was enabled.

CTS: This bit reflects the current status of the clear to send (CTS) modem control input to

UART1.

DSR: This bit reflects the current status of the data set ready (DSR) modem control input to

UART1.

DCD: This bit reflects the current status of the data carrier detect (DCD) modem control input to

UART1.

UBUSY1: UART1 transmitter busy. This bit is set while UART1 is busy transmitting data, it is

guaranteed to remain set until the complete byte has been sent, including all stop bits.

NBFLG: New battery flag. This bit will be set if a low to high transition has occurred on the

nBATCHG input, it is cleared by writing to the STFCLR location.

RSTFLG: Reset flag. This bit will be set if the RESET button has been pressed, forcing the

nURESET input low. It is cleared by writing to the STFCLR location.

PFFLG: Power Fail Flag. This bit will be set if the system has been reset by the nPWRFL input

pin, it is cleared by writing to the STFCLR location.

CLDFLG: Cold start flag. This bit will be set if the CS89712 has been reset with a power on reset,

it is cleared by writing to the STFCLR location.

Table 40. SYSFLG

CS89712 Datasheet(PDF) 86 Page - Cirrus Logic

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