CS89712 datasheet(36/170 Pages) CIRRUS

36 / 170 page

CS89712

DS502PP2

2.17.3

ADC Interface - SSI1 Master Only

The first synchronous serial interface allows inter-

facing to the following peripheral devices:

•

In the default mode, the device is compatible

with the MAXIM MAX148/9 in external clock

mode. Similar SPI- or Microwire-compatible

devices can connect directly to the CS89712.

•

In the extended mode and with negative-edge

triggering selected (the ADCCON and ADC-

CKNSEN bits are set, respectively, in the

SYSCON3 register), this device can be inter-

faced to Analog Devices’ AD7811/12 chip us-

ing nADCCS as a common RFS/TFS line.

•

Other features of the devices, including power

management, can be utilized by software and

the use of the GPIO pins.

The clock output frequency is programmable and

only active during data transmissions to save pow-

er. There are four output frequencies selectable.

The required frequency is selected by program-

ming the corresponding bits 16 and 17 in the

SYSCON1 register. The sample clock (SMPCLK)

always runs at twice the frequency of the shift

clock (ADCCLK). The output channel is fed by an

8-bit shift register when the ADCCON bit of

SYSCON3 is clear. When ADCCON is set, up to

16 bits of configuration command can be sent, as

specified in the SYNCIO register. The input chan-

nel is captured by a 16-bit shift register. The clock

and synchronization pulses are activated by a write

to the output shift register. During transfers the

SSIBUSY (synchronous serial interface busy) bit

in the system status flags register is set. When the

transfer is complete and valid data is in the 16-bit

read shift register, the SSEOTI interrupt is asserted

and the SSIBUSY bit is cleared.

An additional sample clock (SMPCLK) can be en-

abled independently and is set at twice the transfer

clock frequency.

This interface has no local buffering capability and

is only intended to be used with low bandwidth in-

terfaces, such as for a touch-screen ADC interface.

2.17.4

SSI2 with Master / Slave operation

A second SPI / Microwire interface with full mas-

ter/slave capability is provided by the CS89712.

Data rates in slave mode are theoretically up to

512 kbits/s, full duplex, although continuous oper-

ation at this data rate will give an interrupt rate of

2 kHz, too fast for many operating systems. This

would require a worst-case interrupt response time

of less than 0.5 msec and would cause loss of data

through TX underruns and RX overruns.

The interface is fully capable of being clocked at

512 kHz when in slave mode. However, it is antic-

ipated that external hardware will be used to frame

the data into packets. Therefore, although the data

would be transmitted at a rate of 512 kbits/s, the

sustained data rate would in fact only be

85.3 kbits/s (i.e., 1 byte every 750

µsec). At this

SYSCON1

bit 17

SYSCON1

bit 16

18.432–73.728 MHz Operation

ADCCLK Frequency (kHz)

128

Table 25. ADC Interface Operation Frequencies

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