CS89712 datasheet(33/170 Pages) CIRRUS

33 / 170 page

CS89712

DS502PP2

Just prior to the byte being transferred out, PCM-

SYNC goes high for one PCMCLK cycle. Then the

data is shifted out serially to PCMOUT, MSB first,

(with the MSB valid at the same time PCMSYNC

is asserted). Data is shifted on the rising edge of the

PCMCLK output.

Receiving of data is performed by taking data in se-

rially through PCMIN, again MSB first, shifting it

through the shift/load register and loading the com-

plete byte into the receive FIFO. If there is no data

available in the transmit FIFO, then a zero will be

loaded into the shift/load register. Input data is

sampled on the falling edge of PCMCLK. Data is

read from the CODR register.

Note:

After data is transmitted, the speaker amplifier

should be turned off to avoid audible noise. This

is needed because the CS89712 will continue

to transmit data from the FIFO even though it is

empty, thus causing noise. This will occur even

when receiving.

2.17.2

Digital Audio Interface

The DAI interface provides a high quality digital

audio connection to DAI compatible audio devices.

The DAI is a subset of I2S audio format that is sup-

ported by a number of manufacturers.

The DAI interface produces one 128-bit frame at

the audio sample frequency using a bit clock and

frame sync signal. Digital audio data is transferred,

full duplex, via separate transmit and receive data

lines. The bit clock frequency is programmable to

64 fs or 128 fs. The sample frequency (fs) is now

programmable from 8-48Khz using either the on-

chip PLL (73.728MHz) or the external 11.2896

Mhz clock.

The DAI interface contains separate transmit and

receive FIFO’s. The transmit FIFO’s are 8 audio

samples deep and the receive FIFO’s are 12 audio

samples deep.

DAI programming centers around the selection of

the desired sample frequency (fs). All three clocks

(MCLK, LRCK, SCLK) become a multiple of the

selected sample frequency as illustrated on the pre-

vious page. The DAI share the same output with the

CODEC and SSI as shown in Figure 6. Please see

Table 23 for the MUX programming matrix.

2.17.2.1

DAI Operation

Following reset, the DAI logic is disabled. To en-

able the DAI, the applications program should first

clear the emergency underflow and overflow status

bits, which are set following the reset, by writing a

1 to these register bits (in the DAISR register).

Next, the DAI control register should be pro-

grammed with the desired mode of operation using

a word write. The transmit FIFOs can either be

“primed” by writing up to eight 16-bit values each,

or can be filled by the normal interrupt service rou-

tine which handles the DAI FIFOs. Finally, the

FIFOs for each channel must be enabled via writes

to DAIDR2. At this point, transmission/reception

of data begins on the transmit (SDOUT) and re-

Figure 6. Portion of the CS89712 Block Diagram Showing Multiplexed Feature

CODEC

SSI2

DAI 128/64 fs

SSICLK,

SSITXFR,

SSITXDA,

SSIRXDA ,

SSIRSFR

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