CS89712 datasheet(95/170 Pages) CIRRUS

95 / 170 page

CS89712

DS502PP2

3.8 Timer / Counter Registers

3.8.1

TC1D Timer Counter 1 Data Register (address 0x8000.0300)

The timer counter 1 data register is a 16-bit read / write register which sets and reads data to TC1. Any value

written will be decremented on the next rising edge of the clock.

3.8.2

TC2D Timer Counter 2 Data Register (address 0x8000.0340)

The timer counter 2 data register is a 16-bit read / write register which sets and reads data to TC2. Any value

written will be decremented on the next rising edge of the clock.

3.8.3

RTCDR Real-Time Clock Data Register (address 0x8000.0380)

The Real-Time Clock data register is a 32-bit read / write register, which sets and reads the binary time in

the RTC. Any value written will be incremented on the next rising edge of the 1 Hz clock. This register is

reset only by nPOR.

3.8.4

RTCMR Real-Time Clock Match Register (address 0x8000.03C0)

The Real-Time Clock match register is a 32-bit read / write register, which sets and reads the binary match

time to RTC. Any value written will be compared to the current binary time in the RTC, if they match it will

assert the RTCMI interrupt source. This register is reset only by nPOR.

3.9 Miscellaneous Registers

3.9.1

LEDFLSH Register (address 0x8000.22C0)

The output is enabled whenever LEDFLSH[6] = 1. When enabled, PDDDR[0] needs to be configured as an output

pin and the bit cleared to ‘0’ (See Section 3.4.6,

“PDDDR Port D Data Direction Register (address 0x8000.0043)”).

When the LED Flasher is disabled, the pin defaults to being used as Port D bit 0. Thus, this will ensure that the LED

will be off when disabled.

The flash rate is determined by the LEDFLSH[1:0] bits, in the following way:

5:2

1:0

Enable

Duty ratio

Flash rate

LEDFLSH[1:0]

Flash Period (sec)

Table 49. LED Flash Rates

LEDFLSH[5:2]

Duty Ratio

(time on: time off)

LEDFLSH[5:2]

Duty Ratio

(time on: time off)

0000