STV3550 datasheet(120/144 Pages) STMICROELECTRONICS

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STV3550

Reception is stopped by clearing the RxEnable bit of ASC_n_Control. Any currently received

frame is completed including the generation of the receive status flags. Start bits that follow this

frame will not be recognized.

7.8.4.1 Hardware Error Detection

To improve the safety of serial data exchange, the ASC provides three error status flags in the

ASC_n_Status register which indicate if an error has been detected during reception of the last

data frame and associated stop bits.

●

The parity error bit (ParityError) in the ASC_n_Status register is set when the parity check on

the received data is incorrect

In FIFO operation parity errors on the buffers are OR-ed to yield a single parity error bit.

●

The framing error bit (FrameError) in the ASC_n_Status register is set when the RxD pin is

not a 1 during the programmed number of stop bit times (see section 7.8.4)

In FIFO operation the bit remains set while at least one of the entries has a frame error.

●

The overrun error bit (OverrunError) in the ASC_n_Status register is set when the input buffer

is full and a character has not been read out of the ASC_n_RxBuffer register before reception

of a new frame is complete

These flags are updated simultaneously with the transfer of data to the receive input buffer.

Frame and Parity Errors

The most significant bit (bit 9 of 0-9) of each input entry records whether or not there was a frame

error when that entry was received (i.e. one of the effective stop bit values was ‘0’). The

FrameError bit of the ASC_n_Status register is set when the input buffer (double-buffered

operation), or at least one of the valid entries in the input buffering (FIFO-controlled operation), has

its most significant bit set.

If the mode is one where a parity bit is expected, then the next bit (bit 8 of 0-9) records whether

there was a parity error when that entry was received. It does not contain the parity bit that was

received. For 7-bit+parity data frames the parity error bit is set in both the eighth (bit 7 of 0-9) and

the ninth (bit 8 of 0-9) bits. The ParityError bit of ASC_n_Status is set when the input buffer

(double-buffered operation), or at least one of the valid entries in the input buffering (FIFO-

controlled operation), has bit 8 set.

When receiving 8-bit data frames without parity (see section 7.8.2.1), the ninth bit of each input

entry (bit 8 of 0-9) is undefined.

7.8.4.2 Input Buffering Modes

FIFO Enabled Reception

The FIFOs are enabled by setting the FifoEnable bit of the ASC_n_Control register. The input

FIFO is implemented as a 16-deep array of 10-bit vectors (each 9 down to 0). If the input FIFO is

empty i.e. no entries are present, the RxBufFull bit of the ASC_n_Status register is set to ‘0’. If one

or more FIFO entries are present, the RxBufFull bit of the ASC_n_Status register is set to 1. If the

input FIFO is not empty, a read from ASC_n_RxBuffer will get the oldest entry in the input FIFO.

The RxHalfFull bit of the ASC_n_Status register is set when the input FIFO contains more than 8

characters. Writing anything to ASC_n_RxReset empties the input FIFO. As soon as the effective

value of the last stop bit has been determined, the content of the input shift register is transferred to

the input FIFO (except during wake-up mode, in which case this happens only if the wake-up bit, bit

8, is a ‘1’). The receive circuit then waits for the next falling edge transition at the RxD pin.

The OverrunError bit of the ASC_n_Status register is set when the input FIFO is full and a

character is loaded from the input shift register into the input FIFO. It is cleared when the

ASC_n_RxBuffer register is read.

STV3550 Datasheet(PDF) 120 Page - STMicroelectronics

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