STV3550 datasheet(119/144 Pages) STMICROELECTRONICS

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recent entry in the output FIFO. The TxHalfEmpty bit of the ASC_n_Status register is set when the

output FIFO contains 8 or fewer characters.

Values are shifted out of the bottom of the output FIFO into a 9-bit output shift register in order to be

transmitted. If the transmitter is idle (i.e. the output shift register is empty) and something is written

to the ASC_n_TxBuffer so that the output FIFO becomes non-empty, the output shift register is

immediately loaded from the output FIFO and transmission of the data in the output shift register

begins at the next baud rate tick.

When the transmitter is just about to transmit the stop bits, and if the output FIFO is non-empty, the

output shift register will be immediately loaded from the output FIFO, and the transmission of this

new data will begin as soon as the current stop bit period is over (i.e. the next start bit will be

transmitted immediately following the current stop bit period). If the output FIFO is empty at this

point, the output shift register will become empty. Thus back-to-back transmission of data can take

place. If the output FIFO is empty at this point, the output shift register will become empty. Writing

anything to ASC_n_TxReset empties the output FIFO.

After changing the FifoEnable bit, it is important to reset the FIFO to empty (by writing to the

ASC_n_TxReset register), or garbage may be transmitted.

7.8.3.2 Double-buffered Transmission

Double buffering is enabled and the FIFOs disabled by writing 0 to the FifoEnable bit of the

ASC_n_Control register. When the transmitter is idle, the transmit data written into the transmit

buffer ASC_n_TxBuffer is immediately moved to the transmit shift register, thus freeing the

transmit buffer for the next data to be sent. This is indicated by the transmit buffer empty flag

(TxHalfEmpty) being set. The transmit buffer can be loaded with the next data while transmission

of the previous data is still going on.

When the FIFOs are disabled, the TxFull bit is set when the buffer contains 1 character, and a write

to ASC_n_TxBuffer in this situation will overwrite the contents. The TxHalfEmpty bit of the

ASC_n_Status register is set when the output buffer is empty.

7.8.4

Reception

Reception is initiated by a falling edge on the data input pin RxD, provided that the Run and

RxEnable bits of the ASC_n_Control register are set.

Controlled data transfer can be achieved using the RTS handshaking signal provided by the UART.

The sender checks the RTS to ensure the UART is ready to receive data. In double-buffered

reception RTS goes high when ASC_n_RxBuffer is empty, in FIFO-controlled operation it goes

high when RxHalfFull is zero.

The RxD pin is sampled at 16 times the rate of the selected baud rate. A majority decision of the

first, second and third samples of the start bit determines the effective bit value. This avoids

erroneous results that may be caused by noise.

If the detected value of the first bit of a frame is not a 0, then the receive circuit is reset and waits for

the next falling edge transition at the RxD pin. If the start bit is valid, i.e. is 0, the receive circuit

continues sampling and shifts the incoming data frame into the receive shift register. For

subsequent data and parity bits, the majority decision of the seventh, eighth and ninth samples in

each bit time is used to determine the effective bit value. The effective values received on RxD are

shifted into a 10-bit input shift register.

For 0.5 stop bits, the majority decision of the third, fourth, and fifth samples during the stop bit is

used to determine the effective stop bit value. For 1 and 2 stop bits, the majority decision of the

seventh, eighth, and ninth samples during the stop bits is used to determine the effective stop bit

values. For 1.5 stop bits, the majority decision of the fifteenth, sixteenth, and seventeenth samples

during the stop bits is used to determine the effective stop bit value.

STV3550 Datasheet(PDF) 119 Page - STMicroelectronics

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