STV3550 datasheet(121/144 Pages) STMICROELECTRONICS

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After changing the FifoEnable bit, it is important to reset the FIFO to empty by writing to the

ASC_n_RxReset register; otherwise the state of the FIFO pointers may be garbage.

Double-buffered Reception

Double-buffered operation is enabled and the FIFOs disabled by writing 0 to the FifoEnable bit of

the ASC_n_Control register. This mode can be seen as equivalent to a FIFO-controlled operation

with a FIFO of length 1 (the first FIFO vector is in fact used as the buffer). When the last stop bit has

been received (at the end of the last programmed stop bit period) the content of the receive shift

flag (RxBufFull) is set, and the parity (ParityError) and framing error (FrameError) flags are

updated at the same time, after the last stop bit has been received, i.e. at the end of the last stop bit

programmed period. The flags are updated even if no valid stop bits have been received. The

receive circuit then waits for the next falling edge transition at the RxD pin.

7.8.4.3 Time-out Mechanism

The ASC contains an 8-bit time-out counter. This reloads from ASC_n_Timeout whenever one or

more of the following is true:

●

ASC_n_RxBuffer is read

●

the ASC is in the middle of receiving a character

●

ASC_n_Timeout is written to

If none of these conditions hold the counter decrements towards 0 at every baud rate tick.

The TimeoutNotEmpty bit of the ASC_n_Status register is ‘1’ when the input FIFO is not empty

and the time-out counter is zero.

The TimeoutIdle bit of the ASC_n_Status register is ‘1’ when the input FIFO is empty and the time-

out counter is zero.

The effect of this is that whenever the input FIFO has got something in it, the time-out counter will

decrement until something happens to the input FIFO. If nothing happens, and the time-out counter

reaches zero, the TimeoutNotEmpty bit of the ASC_n_Status register will be set.

When the software has emptied the input FIFO, the time-out counter will reset and start

decrementing. If no more characters arrive, when the counter reaches zero the TimeoutIdle bit of

the ASC_n_Status register will be set.

7.8.5

Baud Rate Generation

Each ASC has its own dedicated 16-bit baud rate generator with 16-bit reload capability. The baud

rate generator has two possible modes of operation.

The ASC_n_BaudRate register is the dual-function baud rate generator and reload value register.

A read from this register returns the content of the counter or accumulator (depending on the mode

of operation); writing to it updates the reload register.

If the Run bit of the control register is 1, then any value written in the ASC_n_BaudRate register is

immediately copied to the counter/accumulator. However, if the Run bit is 0 when the register is

written, then the counter/accumulator will not be reloaded until the first subsystem clock cycle after

the Run bit is 1.

The baud rate generator supports two modes of operation, offering a wide range of possible values.

The mode is set via the BaudMode bit in the ASC_n_Control register. Mode 0 is a simple counter

driven by the subsystem clock whereas Mode 1 uses a loop-back accumulator. Mode 0 is

recommended for low baud rates (below 19.2K baud), where its error deviation is low, and Mode 1

is recommended for baud rates above 19.2 K.

STV3550 Datasheet(PDF) 121 Page - STMicroelectronics

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