AMD-766AC datasheet(21/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

4.3.4.2.2

The IRQ lines

The IOAPIC supports 24 interrupt request signals. Each interrupt request input is combined with its corresponding

redirection register to specify the behavior of the interrupt. These interrupt request signals are connected to

redirection registers (APIC IRQs) as shown in the following table.

APIC IRQ Connection

PIC INTR output

PIC_IRQ12

PIC_IRQ1

PIC_IRQ13 (floating point error)

PIC_IRQ0 (PIT)

PIC_IRQ14

PIC_IRQ3

PIC_IRQ15

PIC_IRQ4

PIRQA#

PIC_IRQ5

PIRQB#

PIC_IRQ6

PIRQC#

PIC_IRQ7

PIRQD#

PIC_INT8 (RTC)

GPIO2 (see PMC2)

PIC_IRQ9

GPIO3 (see PMC3)

PIC_IRQ10

SCI or GPIO16 (see C0A4B and PMD0)

PIC_IRQ11

SMI or GPIO17 (see C0A4B and PMD1)

Note: APIC IRQs [23:20] may also be ORed with the TCO IRQ as specified by C3A44[TCO_INT_SEL]. Note:

PIC_IRQx is specified in section 4.3.4.1.

4.3.5

Real-Time Clock (Logic Powered by VDD_AL)

The real-time clock logic requires an external 32 kHz oscillator connected to RTCX_IN and RTCX_OUT. It

includes a clock and calendar timer, an alarm (which generates an interrupt), and 256 bytes of non-volatile RAM. It

is register compatible with the legacy PC real-time clocks. It meets ACPI real-time clock requirements. The real-

time clock resides on the VDD_AL power plane.

4.4

Enhanced IDE Controller

The enhanced IDE controller support independent primary and secondary ports. Each port supports two drives.

Supported protocols include PIO modes 0-4, multi-word DMA, and ultra DMA modes through to ATA-100. Each of

the four possible drives may be programmed to operate in any mode independent of the other drives.

The enhanced IDE controller is accessed through function 1 PCI configuration registers (C1Axx).

4.5

USB Controller

The USB Controller is an implementation of the Open Host Controller Interface 1.0a specification containing a host

controller core, a 4-port root hub, and hardware traps for legacy keyboard and mouse emulation.

4.5.1

USB Interrupts

The USB interrupt signal is drive low the PCI interrupt, PIRQD#. However, it may be diverted to SMIs by the

OHCI-defined register HcControl_InterruptRouting. See section 4.3.4.1 for data on routing keyboard and mouse

emulation interrupts. SMI interrupts are also generated in response to accesses to IO ports 60h and 64h and to IRQ1

and IRQ12 in support of the emulation logic.

AMD-766AC Datasheet(PDF) 21 Page - Advanced Micro Devices

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