AMD-766AC datasheet(13/96 Pages) AMD

13 / 96 page

Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

Pin name and description

IO cell

type

Power

plane

During

Reset

Post

Reset

POS

a power button override event is generated. A power button override event

causes the PWRON# pin to be driven high and PM00[PBOR_STS] to be

set high. The logic for this pin includes a 16 millisecond debounce circuit;

the signal must be stable for about 16 milliseconds before it is detected by

the rest of the internal logic.

PWRGD. Power good. This is required to be low while the VDD3 power

plane is not valid, stay low for at least 50 milliseconds after it becomes

valid, and then go high. It is the reset source for the VDD3 logic in the IC.

The rising edge of this pin is debounced for one to two 32 kHz (RTC)

clocks before it is internally detected as being high.

Input

w/H

VDD_

AUX

---

PWRON#. Main power on. This is designed to control the main power

supplies to the system board, including the IC’s VDD3 plane. It is asserted

during the FON, C2, C3, and POS states; it is deasserted during the STR,

STD and SOFF states. See section 4.6.1.5 for more details.

VDD_

AUX

Low

RI#. Ring indicate. This pin may be used to generate SMI or SCI

interrupts and resume events. It controls PM20[RI_STS]. This pin may

also be configured as GPIO14 by PMCE.

Input,

VDD_

AUX

---

RPWRON. RAM power on. This is designed to control power to the

system memory power plane. When high, it is expected that power to

system memory is enabled. When low, it is expected that power to system

memory is disabled. This pin is low during STD and SOFF and high in all

other states. See section 4.6.1.5 for more details.

VDD_

AUX

High

RTCX_IN. Real time clock 32.768 kHz crystal input. This pin is

designed to be connected through a crystal oscillator to RTCX_OUT.

Analog VDD_

Func.

RTCX_OUT. Real time clock 32.768 kHz crystal output.

Analog VDD_

Func.

SERIRQ. Serial IRQ function. This pin supports the serial IRQ protocol.

Control for this is in C3A4A.

VDD3

Func.

SLPBTN#. Sleep button. This may be used to control the automatic

transition from a sleep state to FON. It controls PM00[SLPBTN_STS].

Also, if it is asserted for four seconds from any state other than SOFF, then

a power button override event is generated. A power button override event

causes the PWRON# pin to be driven high and PM00[PBOR_STS] to be

set high. The logic for this pin includes a 16 millisecond debounce circuit;

the signal must be stable for about 16 milliseconds before it is detected by

the rest of the internal logic. This pin may also be configured as GPIO3 by

PMC3.

Input,

VDD_

AUX

---

SMBUSC. System management bus (SMBus) clock. This pin may also

be configured as GPIO0 by PMC0.

I w/H /

VDD_

AUX

3-state 3-state

Func.

SMBUSD. System management bus (SMBus) data. This pin may also be

configured as GPIO1 by PMC1.

I w/H /

VDD_

AUX

3-state 3-state

Func.

SUSPEND#. Suspend output. This may be used during the POS state to

control an external power planes. It is controlled by C3A50.

VDD3

High

Func.

THERM#. Input; thermal warning detect. This may be used to

automatically enable processor throttling as specified by C3A50[TTH_EN,

TTH_RATIO]. See section 4.6.1.4 for more details.

VDD3

Func.

AMD-766AC Datasheet(PDF) 13 Page - Advanced Micro Devices

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